Telephonic communications – Substation or terminal circuitry – Sidetone control or hybrid circuit
Reexamination Certificate
2000-08-24
2004-12-28
Isen, Forester W. (Department: 2644)
Telephonic communications
Substation or terminal circuitry
Sidetone control or hybrid circuit
C379S392000, C379S406010, C379S392010, C379S390020, C379S406150, C379S406020, C370S276000
Reexamination Certificate
active
06836544
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The described invention relates to the field of communications. In particular, the invention relates to a method and apparatus for reducing echo in a full duplex transceiver system.
2. Description of Related Art
In a full duplex transceiver system, the output of the transmitter and the input of the receiver share the same path for connecting to an external data line. The transmitter's transmission is thus received at the input of the receiver producing an “echo”, and a way of reducing this echo is employed so as not to interfere with the correct reception of signals by the receiver.
Various digital subscriber lines (DSL) as well as some Ethernet lines support full duplex transceiver systems. For example, the Gigabit Ethernet (IEEE specification 802.3) supports a full duplex transceiver system, and the 10 Gigabit Ethernet specification, although not yet adopted, is also likely to support a full duplex transceiver system.
One prior art method of reducing the echo is performed by subtracting a replica current from the receiver, as will be shown with respect to FIG.
1
. The replica current is typically a predetermined fraction of the transmitter current.
As shown in
FIG. 1
, transmitter
19
provides currents +ITX and −ITX on input/output (I/O) lines
10
and
12
, respectively. The I/O lines are also coupled to a receiver
20
.
FIG. 1
shows only the input stage of the receiver
20
, which comprises resistors
22
,
24
,
46
, and
48
, capacitors
60
and
62
, and an operation amplifier (op amp)
30
. Resistors
22
and
24
each have values M*RT and couple the I/O lines
10
and
12
to the op amp
30
via a differential circuit path that carries differential current I
FB
The inputs of the op amp
32
and
34
are coupled to differential replica current paths
42
and
44
that carry a differential current ITX/N−(−ITX/N)=2 ITX/N.
Two feedback resistors R
FB
46
and
48
couple the inputs
32
and
34
of the op amp
30
to its outputs
52
and
54
, respectively. Capacitors
60
and
62
also couple the inputs
32
and
34
of the op amp
30
to its outputs
52
and
54
.
The transmitter and receiver are generally on the same semiconductor chip and a termination resistor R
T
70
is off-chip to match the impedance of a data line
80
such as a DSL or Gigabit Ethernet line. A transformer
90
couples the data line
80
to the I/O lines
10
and
12
. A circuit board is typically used to mount the semiconductor chip, transformer
90
, and resistor R
T
70
. A center tap
92
of the transformer
90
is coupled to the power supply of the circuit board. This center tap provides the differential current for the transmitter shown as +ITX and −ITX in FIG.
1
.
For the circuit shown in
FIG. 1
, using the condition N=4M+1, it will now be shown that the dc output signal at the op amp output is just equal to the received signal from the external data line:
The transmitter voltage, in the absence of any received signal (i.e., for V
RX
=0), is given by the equations:
V
TX
=I
TX
R
L
, where the load across the transmitter is given by:
R
L
=
R
T
&LeftDoubleBracketingBar;
R
0
&RightDoubleBracketingBar;
2
MR
T
=
(
2
MR
0
/
4
M
+
1
)
,
where
R
T
=
R
0
.
The differential voltage V
MX
across the I/O lines
10
and
12
as shown in
FIG. 1
is made up of the voltage component contributed by the transmitter and the voltage component contributed by the receiver:
V
MX
=
V
TX
+
V
RX
=
(
2
MR
0
/
4
M
+
1
)
I
TX
+
V
RX
The differential current flowing through the resistors M R
T
22
and
24
is given by the equation:
I
FB
=
V
MX
/
MR
T
=
(
2
/
(
4
M
+
1
)
)
I
TX
+
(
V
RX
/
MR
0
)
,
where
R
T
=
R
0
.
The differential replica current leaving the receiver through replica current paths
42
and
44
is given by the equation:
I
RD
=−2
I
TX
/N
The output of the op amp
30
is:
V
OUT
=
[
I
FB
+
I
RD
]
R
FB
=
[
(
2
/
(
4
M
+
1
)
)
I
TX
-
(
2
/
N
)
I
TX
+
(
V
RX
/
MR
0
)
]
R
FB
=
V
RX
,
where
N
=
4
M
+
1
and
R
FB
=
MR
0
Thus, the output of the op amp
30
is just the received signal from the external data line. However, although the above description holds for a dc signal, this may not be the case for all frequencies.
REFERENCES:
patent: 3602648 (1971-08-01), Holtz
patent: 4002857 (1977-01-01), Herlacher
patent: 4236048 (1980-11-01), Olney
patent: 4807225 (1989-02-01), Fitch
patent: 5333176 (1994-07-01), Burke et al.
patent: 5396549 (1995-03-01), Mulder et al.
patent: 5533119 (1996-07-01), Adair et al.
patent: 6400772 (2002-06-01), Chaplik
patent: 6417687 (2002-07-01), Heinrich
Allstot et al “An Electrically-Programmable Switched Capacitor Filter”, IEEE Journal of Solid-State Circuits, vol. SC -14 No. 6, Dec. 1979, pp. 1034-1041.
Isen Forester W.
Singh Ramnandan
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