Active solid-state devices (e.g. – transistors – solid-state diode – Specified wide band gap semiconductor material other than... – Diamond or silicon carbide
Reexamination Certificate
2002-03-07
2004-05-11
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Specified wide band gap semiconductor material other than...
Diamond or silicon carbide
C257S627000, C257S628000, C257S194000
Reexamination Certificate
active
06734461
ABSTRACT:
TECHNICAL FIELD
This invention relates to a SiC wafer suited to semiconductor electronic parts, to a SiC semiconductor device equipped with this SiC wafer, and to a method for manufacturing a SiC wafer.
BACKGROUND ART
Recent years have witnessed a great deal of research into compound semiconductors made from light elements, such as silicon carbide (SiC) and gallium, nitride (GaN). Because they are made from light elements, such compound semiconductors have high bonding energy, and as a result they are characterized by a large energy forbidden band width (band gap), dielectric breakdown field, and thermal conductivity. Thanks to this wide band gap, these compound semiconductors are drawing attention as materials for power devices of high efficiency and high voltage resistance, high frequency power devices, devices with high operating temperatures, and devices that emit blue to ultraviolet light. However, because of their high bonding energy, these compounds do not melt even at high temperature at atmospheric pressure, making it difficult to grow bulk crystals by recrystallization of a melt, which is used with other semiconductors such as silicon (Si).
For instance, using SiC as a semiconductor material requires that high-quality single crystals of a certain size be obtained. Consequently, pieces of SiC single crystals used to be obtained by a method that makes use of a chemical reaction, called the Atchison process, or a method that makes use of sublimation recrystallization, called the Rayleigh process.
Today, single crystals of silicon carbide produced by these methods are used for substrates, over which SiC ingots are grown by a modified Rayleigh process involving sublimation recrystallization, and these SiC ingots are then sliced and mirror polished to manufacture a SiC substrate. On this substrate are grown SiC single crystals of the targeted scale by vapor phase epitaxial growth or liquid phase epitaxial growth, thereby forming an active layer of controlled film thickness and impurity density, and this product is used to produce SiC semiconductor devices such as pn junction diodes, Schottky diodes, and various types of transistors.
Nevertheless, of the above methods, the Atchison process involves heating a mixture of quartz and coke in an electric furnace, and precipitating crystals by spontaneous nucleation, so the impurity content is high, and it is difficult to control the crystallographic plane and shape of the resulting crystals. The Rayleigh process also involves growing crystals by spontaneous nucleation, which again makes it difficult to control the crystallographic plane and shape of the crystals.
With the modified Rayleigh process, such as with the invention disclosed in Japanese Patent Publication S59-48792, a large SiC ingot is obtained in the form of a single crystal polymorph. However, this ingot usually contains large defects called micropipes (small holes that go through in the <0001> axial direction), in a density of about 1 to 50 cm
−2
. There are also screw dislocations having a Burger's vector in the c axial direction in a density of about 10
3
to 10
4
cm
−2
.
A substrate having a SiC {0001} plane, or provided with an off angle of 3 to 8 degrees from this plane, is usually used for epitaxial growth. It is known that most of the micropipe defects or screw dislocations. present in a substrate pass through to the SiC epitaxial growth layer, and that the device characteristics will be markedly inferior if a SiC device produced using an epitaxial growth layer contains micropipe defects. Micropipe defects are therefore the greatest obstacle to manufacturing a large capacity (large current and high voltage resistance) SiC semiconductor device at a high yield.
When homoepitaxial growth of SiC is performed using an ordinary SiC substrate having a SiC {0001} plane, or having an off angle of several degrees from this plane, atomic step bunching tends to occur on the crystal surface. If the extent of this step bunching is large, there is an increase in the surface roughness of the SiC epitaxial growth layer, and the flatness suffers at the metal-oxide-semiconductor (MOS) interface, so there is a decrease in the inversion layer channel mobility of an MOS field effect transistor (MOSFET). Flatness also suffers at a pn junction or Schottky barrier interface, field bunching occurs at the junction interface, and this leads to problems such as decrease voltage resistance and increased leakage current.
There are numerous crystal polymorphs of SiC. Of these, the 4H polytype (4H—SiC) has high mobility, and its donor and acceptor ionization energy is low, which means that this might be an ideal SiC polytype for the production of SiC semiconductor devices. Nevertheless, when an inversion type of MOSFET is fabricated using an epitaxial growth layer over a substrate having a 4H—SiC {0001} plane, or provided with an off angle of 3 to 8 degrees from this plane, the channel mobility is extremely low, about 1 to 20 cm
2
/Vs, and this precludes obtaining a high performance transistor.
In an effort to solve these problems, Japanese Patent Publication 2,804,860 discloses performing growth by the modified Rayleigh process using seed crystals having a plane other than the (0001) of SiC, such as a (1-100) plane, so as to obtain a SiC ingot with fewer micropipes. When epitaxial growth is. performed over a SiC (1-100) plane, however, this tends to result in stacking faults, which are planar defects that occur during growth, making it difficult to obtain SiC single crystals that are high enough in quality for the production of semiconductor devices.
In addition to the use of a SiC (1-100) substrate, research has also been conducted in recent years into producing SiC wafers using a 6H polytype SiC (11-20) substrate. When this 6H polytype SiC (11-20) substrate is used, micropipes and screw dislocations extending in the <0001> axial direction do not reach the epitaxial layer on the substrate, which affords a reduction in micropipe defects within this epitaxial layer.
DISCLOSURE OF THE INVENTION
However, the following problems have been encountered with SiC wafers produced using the above-mentioned 6H polytype SiC (11-20) substrate. When a SiC epitaxial layer is grown over a conventional SiC (11-20) substrate, strain develops at the interface between the SiC epitaxial growth layer and the SiC substrate due to lattice mismatching attributable to the difference in impurity densities. This strain adversely affects the crystallinity of the epitaxial growth layer, and hampers efforts to produce a high-quality SiC epitaxial growth layer.
Furthermore, the anisotropy of electron mobility becomes a problem when a device is fabricated using a 6H polytype SiC (11-20) substrate. Specifically, among the 6H—SiC crystals, the electron mobility in the <0001>axial direction is only about 20 to 30% of the mobility in the <1-100> and <11-20> directions. Accordingly, anisotropy is three to five times greater for the in-plane electrical conduction of a growth layer on a 6H—SiC (11-20) plane. Still another problem is that the stacking faults tend to be exposed on the surface in the case of the (1-100) plane or (11-20) plane.
The present invention was conceived in light of this situation, and it is an object thereof to provide a SiC wafer with which there is less anisotropy in electron mobility when used as a semiconductor device, and less strain is caused by lattice mismatching between the SiC substrate and the SiC epitaxial growth layer, as well as a semiconductor device provided with this wafer, and a method for manufacturing a SiC wafer.
In order to achieve the stated object, the SiC wafer according to the present invention is characterized in that it comprises a 4H polytype SiC substrate in which the crystal plane orientation is substantially {03-38}; and a buffer layer composed of SiC formed over the SiC substrate.
Also, the method for manufacturing a SiC wafer according to the present invention is characterized in that a
Kimoto Tsunenobu
Matsunami Hiroyuki
Shiomi Hiromu
Eckert George
McDermott & Will & Emery
Nguyen Joseph
Sixon Inc.
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