SiC/Si heterostructure semiconductor switch and fabrication...

Details SiC/Si heterostructure semiconductor switch and fabrication... SiC/Si heterostructure semiconductor switch and fabrication...

1998-07-21

2001-08-07

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Specified wide band gap semiconductor material other than...

Diamond or silicon carbide

C257S191000

Reexamination Certificate

active

06271544

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to a SiC/Si heterostructure negative-differential-resistance (NDR) diode, and in particular related to a SiC/Si heterostructure semiconductor switch.
BACKGROUND OF THE INVENTION
In addition to be applied for logic, memory and functional device circuits, the N-shaped negative-differential-resistance (NDR) device has been used as a special-application switch. To offer an effective switching action, a switch should have two stable operating states, the high-current, low-voltage “on-state” and the low-current, high-voltage “off-state”). The switch with these two stable operating states will have low off-state power dissipation, and a large on/off current ratio. Such performance can only be achieved from a low-impedance on-state and a high-impedance off-state. In general, a S-shaped NDR device is more suitable for use as a semiconductor switch in view of its low on-state impedance and high off-state impedance. However, most of the S-shaped NDR devices are of a PNPN multi-layer structure, and thus the fabrication process thereof is complicated and difficult.
For most conventional N-shaped NDR devices, such as tunneling diode and resonant tunneling diode, the off-state impedance is small. Hence, when acting as switches, they will suffer a low on/off current ratio and high power loss at the off-state due to a large off-state current. The on/off current ratio is determined by the peak-to-valley current ratio (PVCR) which is not high for most conventional N-shaped NDR devices. Therefore, the switching action is not obvious when the conventional N-shaped NDR devices are used as a switch. In addition, the selections of bias and load of the switches are restricted in a great extent. In order to enhance the PVCR, some N-shaped NDR devices were modified to have more complicated structures, for examples &dgr;-doping layers, double quantum wells, tunneling devices and integrated transistors. However, these modified structures require more sophisticated fabrication techniques and thus increase the difficulty of fabrication.
The main objective of the present invention is to provide a N-shaped NDR semiconductor switch having a simple structure which is easy to be made, and an excellent switching performance similar to the S-shaped NDR semiconductor switch. More specifically, the N-shaped NDR semiconductor switch of the present invention will be devoid of the following drawbacks of the prior art:
1. the high off-state power dissipation and low on/off current ratio of the conventional N-shaped NDR semiconductor switch;
2. the complicated structures of the conventional N-shaped NDR semiconductor switch and the conventional S-shaped NDR semiconductor switch, and the difficult fabrication processes thereof; and
3. the relatively high price of the conventional N-shaped NDR semiconductor switch and the incompatibility with the fabrication processes of Si integrated circuits resulting from its III-V structure, and the problem of not able to work at high temperature (>100° C.).
SUMMARY OF THE INVENTION
In order to accomplish the objectives of the present invention a SiC/Si heterostructure semiconductor switch constructed according to the present invention comprises a single crystal silicon (Si) layer, a silicon carbide (SiC) layer and a graded-composition layer between the Si layer and the SiC layer. The graded-composition layer contains Si and C, wherein Si/C molar ratio decreases with increasing distance from the Si layer. The Si layer may be doped with impurities of the first conductive type, preferably n-type impurities, and the SiC layer may be doped with impurities of the second conductive type, preferably p-type impurities.
The semiconductor switch of the present invention may further comprise a first electrode formed on a surface of the Si layer which is opposite to and away from the graded-composition layer, and a second electrode formed on a surface of the SiC layer which is opposite to and away from the graded-composition layer.
Preferably, the graded-composition layer has a thickness of 2000-3000 Å.
Preferably, the SiC layer has a thickness of 5000-7000 Å.
A method for preparing the SiC/Si heterostructure semiconductor switch of the present invention is also disclosed, which comprises the following steps:
a) removing a native oxide on a single crystal silicon (Si) substrate doped with impurities of a first conductive type;
b) forming a graded-composition layer on a surface of the Si substrate from the step a) in a reaction chamber by chemical vapor deposition, wherein a fixed flow rate of silane gas is introduced into the reaction chamber and a gradually increasing flow rate of alkane gas is introduced into the reaction chamber during the chemical vapor deposition, wherein the flow rate of the alkane gas is zero when the chemical vapor deposition is initiated; and
c) forming a silicon carbide (SiC) layer doped with impurities of a second conductive type on the graded-composition layer.
Preferably, the method of the present invention further comprises a step of cleaning the single crystal silicon (Si) substrate doped with the first conductive type impurities prior to the step a).
Preferably, in the step a) the single crystal silicon (Si) substrate doped with the first conductive type impurities is placed in a mixture of HCl and H
2
at 2.5 torr and 900° C. for a period of time to remove the native oxide.
Preferably, the silane gas is SiH
4
and the alkane gas is C
3
H
8
in the step b).
Preferably, SiH
4
as the silane gas is introduced into the reaction chamber at 12 sccm and C
3
H
8
as the alkane gas is introduced into the reaction chamber with a gradually varied flow rate from 0 to 10 sccm during the chemical vapor deposition in the step b), wherein the reaction chamber is maintained at 1200° C. and 2.5 torr with an additional H
2
stream being introduced into the reaction chamber.
Preferably, in the step c) the silicon carbide (SiC) layer doped with the second conductive type impurities is formed on the graded-composition layer in a reaction chamber which is maintained at 1200° C. and 2.5 torr, wherein a C
3
H
8
stream, a B
2
H
6
stream, a SiH
4
stream and a H
2
stream are introduced into the reaction chamber at flow rates of 10 sccm, 12 sccm, 12 sccm and 1.2 lpm (liter per minute) respectively.
Preferably, the method of the present invention further comprises steps of forming a first electrode on a surface of the Si substrate which is opposite to and away from the graded-composition layer; and forming a second electrode formed on a surface of the SiC layer which is opposite to and away from the graded-composition layer after the step c).


REFERENCES:
patent: 5670414 (1997-09-01), Fang et al.
patent: 6077760 (2000-06-01), Fang et al.

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