SIC field-effect transistor array with ring type trenches and me

Details SIC field-effect transistor array with ring type trenches and me SIC field-effect transistor array with ring type trenches and me

1996-02-28

1998-05-05

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Specified wide band gap semiconductor material other than...

Diamond or silicon carbide

257623, 257334, H01L 310312

Patent

active

057478317

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention relates to an arrangement of SiC field-effect transistors and a method of producing them.
Because of its large band gap, SiC has proven suitable for high voltage, and different proposals have been made for embodying field-effect transistors for high voltages.
In silicon technology, it is known to use the "surface-gate technology" described in the book by B. Jayant Baliga, "Modern Power Devices," N.Y., 1987. In order to produce the gate regions of power JFETs, it is not particularly favorable to use the planar technique. Regardless of whether the silicon technique or SiC technique is used, an arrangement of the masks which does not provide precise coverage leads to short circuits if the typical dimensions of the components are used. Nevertheless, in order to maintain the necessarily small dimensions of the components for good blocking ability, it is proposed in the above-cited book to sink the gate. As is readily apparent, this arrangement of the gate contact in a vertical trench, into whose walls boron diffuses, has technological advantages. In particular, the attachment of the gate contact by means of metallization is facilitated by the fact that the metal hardly precipitates on the walls, which saves a separate masking step.
of course, it is desirable to transfer this technique to SiC material. However, there are various difficulties associated with this. diffusion occurs in SiC at the conventional processing temperatures. structures can be reduced by a factor of 5 to 10. A corresponding lateral scaling approaches the limits of the masking technique. If the geometrical channel width cannot be scaled down accordingly, the pinch-off behavior worsens.
The object of the invention is to provide a structure for field-effect transistors in which a sufficient pinch-off behavior can be achieved in the channel zone by the smallest possible gate voltage.


SUMMARY OF THE INVENTION

The above object generally is achieved according to the present invention by an arrangement of SiC field-effect transistors having a source contact, a gate contact and a drain contact disposed on a semiconductor wafer, wherein the source contacts are disposed on the surface of the semiconductor wafer, the drain contacts are disposed on the underside of the semiconductor wafer, the gate contacts are disposed in trench-shaped structures, with the trench-shaped structures surrounding the individual source electrodes of the field-effect transistors in ring fashion, and with the gate contacts being connected to one another on the bottom of the trenches.
Modifications of the invention and a method of producing the field-effect transistors according to the invention are likewise disclosed.
The essential nature of the invention is that the components no longer have a striated structure, but are configured to be rotationally symmetrical. Because of this, the pinch-off of the channel can be effected from all sides of the annular gate contact on the trench bottom, beginning from the side walls. Because diffusion is not possible, the doping is preferably performed by means of ion implantation. This is particularly simple if the mesa-shaped component has inclined side walls. Because of the inclined side walls, doping is easily possible through ion implantation with boron or other trivalent dopants. The mesa-shaped components are switched in parallel in order to attain greater outputs. The gate contacts are guided in the trenches, the source contacting is effected on the top side of the silicon wafer and the drain connection is attached to the underside.
The invention is described in detail below in conjunction with the drawing.


BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic representation of an embodiment of the components in plan view;
FIGS. 2a-2h schematically illustrate the production method in different phases;
FIG. 3 shows a simplified structure of the individual component for simulation calculations, and
FIGS. 4a and 4b shows the results of simulation calculations for two different geometri

REFERENCES:
patent: 4262296 (1981-04-01), Shealy et al.
patent: 4941026 (1990-07-01), Temple
patent: 4947218 (1990-08-01), Edmond et al.
patent: 5323040 (1994-06-01), Baliga
patent: 5391895 (1995-02-01), Dreifus
patent: 5396085 (1995-03-01), Baliga
patent: 5506421 (1996-04-01), Palmour
Osamu Ozawa et al, "A vertical FET with Self-Alighned Ion-Implantated Source and Gate Regions" (see whole document).
ESSDERC '91: 21st European Solid State Device Research Conference, Montreux, Switzerland, 16-19 Sep. 1991, Microelectronic Engineering, Oct. 1991, Netherlands (see whole document).

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