Textiles: manufacturing
Reexamination Certificate
2002-10-01
2003-12-23
Ng{haeck over (o)}, Ng{haeck over (a)}n V. (Department: 2814)
Textiles: manufacturing
C257S137000, C257S146000, C257S163000
Reexamination Certificate
active
06666481
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices including thyristors and implementations thereof including memory, current-switching applications and others.
BACKGROUND
An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price), with DRAM cell size being typically between 6 F
2
and 8 F
2
, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor peeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and is typically between about 60 F
2
and 100 F
2
.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin capacitively-coupled thyristor-type NDR device can be effective in overcoming many previously unresolved problems for thyristor-based applications. An important consideration in the design of the thin capacitively-coupled thyristor device involves designing the body of the thyristor sufficiently thin, so that the capacitive coupling between the control port and the thyristor base region can substantially modulate the potential of the base region. Another important consideration in semiconductor device design, including those employing thin capacitively-coupled thyristor-type devices, includes forming devices in applications where electrical connection needs to be made to portions of the device buried in a substrate. For instance, it may be advantageous to form a vertical thyristor having portions thereof buried in the substrate and to which electrical access is desirable.
These and other design considerations have presented challenges to efforts to implement such a thin capacitively-coupled thyristor in bulk substrate applications, and in particular in highly dense applications.
SUMMARY
The present invention is directed to overcoming the above-mentioned challenges and others related to the types of devices and applications discussed above, including memory cells, as well as in other circuits. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor device includes a thyristor (i.e., thyristor-based) having a buried emitter region in a substrate, and a current shunt in the substrate and coupled to the buried emitter region. The current shunt extends from the buried emitter region, through the substrate and to a node at the upper surface of the substrate. The thyristor includes a control port arranged for capacitively coupling to the thyristor for controlling current flow therein (e.g., wherein the control port is adapted for causing an outflow of minority carriers from a region of the thyristor in response to at least one voltage pulse applied thereto). With this approach, contact to a buried emitter region of the thyristor can be made, for example, via the node at the upper surface, addressing challenges including those discussed hereinabove.
In another example embodiment of the present invention, the control port is formed in a filled trench adjacent to the thyristor and lined with a dielectric, and the control port is capacitively coupled to the thyristor via the dielectric. In one approach, the control port is near a bottom portion of the filled trench; this approach has also been found to be useful in filling lower portions of the filled trench when the trench has a high height-to-width aspect ratio. In another implementation, the filled trench has a varied depth, with a relatively deeper portion thereof electrically insulating the buried emitter region from adjacent circuitry in the device. In yet another implementation, the semiconductor device includes a shallow trench isolation (STI) region in the substrate, with a relatively deeper portion of the filled trench being below the STI region. In still another implementation, the filled trench also includes the current shunt, with an insulative material electrically insulating the current shunt from the control port.
According to another example embodiment of the present invention, a semiconductor device includes a conductive shunt electrically connecting a buried emitter region of a thyristor with a pass device. The thyristor includes a body having the buried emitter region at a bottom portion of the thyristor that is buried below and upper surface of a substrate, and a control port adapted for capacitively coupling to the body for controlling current in the thyristor. The pass device is formed at the upper surface of the substrate, adjacent to the thyristor and having source/drain regions separated by a channel region in the substrate, with a gate capacitively coupled to the channel region. The conductive shunt is formed extending through a portion of the substrate and vertically between the emitter region and the first source/drain region, thus electrically connecting the pass device and the emitter region where the emitter region is buried in the substrate. Connecting to a buried emitter using this approach has also been found to be useful, for example, in memory and/or other applications wherein electrical access to a buried emitter region is desirable.
In a more particular example embodiment of the present invention, the conductive shunt is used to form the buried emitter region. The conductive shunt is doped with a dopant that is out-diffused from the conductive shunt into the substrate below and adjacent to the trench. The diffused dopant forms the emitter region of the thyristor, which is electrically connected to the conductive shunt. The conductive shunt is also electrically coupled to the first source/drain region, forming an electrical connection between the buried emitter region and the first source/drain region.
In another example embodiment of the present invention, a plurality of semiconductor devices including thyristors, such as those discussed above, are configured and arranged as a memory array adapted for read and write access. Each thyristor includes a buried emitter region
Horch Andrew
Robins Scott
Ng{haeck over (o)} Ng{haeck over (a)}n V.
T-Ram, Inc.
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