Shunt circuit for electrostatic discharge protection

Details Shunt circuit for electrostatic discharge protection Shunt circuit for electrostatic discharge protection

1992-02-04

1994-02-15

DeBoer, Todd

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 361 91, 257357, H02H 904

Patent

active

052872416

ABSTRACT:
A circuit is added to a complementary metal-oxide silicon (CMOS) integrated circuit (IC) to provide an intentional, non-reverse-biased VDD-to-VSS shunt path for transient currents such as electrostatic discharges (ESD). This circuit protects the IC from ESD damage by turning on before any other path, thus directing the ESD transient current away from easily damaged structures. Specifically, the ESD transient current is steered from the VDD rail to the VSS rail through the on conduction of a P-channel transistor whose source and drain are connected to VDD and VSS respectively. The voltage on the gate of this transistor follows the VDD supply rail because it is driven by a delay network formed by a second transistor and a capacitor. This VDD-tracking delay network turns the VDD-to-VSS transistor on during a transient and off during normal operation of the IC.

REFERENCES:
patent: 4595941 (1986-06-01), Avery
patent: 5189588 (1993-02-01), Yano et al.

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