Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2002-08-22
2004-07-13
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S144000, C341S118000
Reexamination Certificate
active
06762702
ABSTRACT:
BACKGROUND OF THE INVENTION
In high resolution digital-to-analog converters (DACs), performance metrics such as linearity and noise are nominally determined by the matching of parameters derived from physical quantities in the construction of the DACs on an integrated circuit (IC), such as width, length, thickness, doping, etc. As a general rule, for each additional bit of performance in the DAC, parameter matching needs to be twice as tight. This translates to an increase by a factor of four in the IC area required by the DAC. When the DAC resolution is in the 16-bit range, it is no longer practical/economical to use size alone to achieve the required matching.
Over-sampled (sigma-delta) DACs (also referred to as “converters”) alleviate the need for raw matching using single-bit conversion (so called 1-bit DACs in CD players). A single-bit DAC has only two points in a transfer function of the DAC, and thus is inherently linear. The function of a sigma-delta modulator with a one-bit quantizer is to approximate a high resolution low frequency signal with a high frequency two-level signal. The drawback here is this produces large amounts of out-of-band, for example, high frequency, noise.
One solution is to use more than two levels of quantization. For example, 17 levels may be used. However, now linearity requirements are to the full resolution of the DAC. That is, for a 16-bit DAC, the transfer function of the DAC with these quantization levels must be collinear to 1 part in 2
16
, which is 1 part in 65,536. Such linearity is difficult to achieve with raw parameter matching of the single-bit DACs. Thus, there is need to achieve such linearity in a multi-level DAC using an alternative to raw parameter matching.
SUMMARY OF THE INVENTION
For high resolution over-sampled DACs, where the signal frequency band is much smaller than the sample rate of the DAC, there exists an opportunity to apply what is referred to as dynamic element matching to lessen the requirement for raw device matching. This is an entirely digital technique that operates on logic signals. Nominally, without dynamic element matching, mismatched single-bit DAC devices generate errors across all frequency bands, including low frequencies where the signals of interest reside. With dynamic element matching, these errors at the low frequencies (that is, in low frequency bands) are modulated to higher frequencies, outside the signal band of interest, where they can be substantially eliminated with a lowpass filter.
The present invention uses dynamic element matching of the single-bit DACs in a multi-bit DAC, to get full multi-bit (for example, 16-bit) accuracy. The main idea of dynamic element matching is to make each equally weighted unit element (that is, each single-element DAC) in the DAC perform equal work. For direct-current (DC) signals (that is, signals at zero Hz), the cancellation is perfect or nearly perfect. For low frequency signals, the errors are filtered with a 1st order highpass transfer function equal to (1−z
−1
) in the frequency domain. In particular, the transfer function approximates sin(&pgr; f
s
/2)/(&pgr; f
s
/2), where f
s
is the sample frequency.
The higher the over-sample ratio (where the over-sample ratio is defined as the sample frequency of the sigma-delta modulator over the signal frequency), the more effectively dynamic element matching can modulate the mismatch noise to out of band frequencies, that is, to frequencies away from the frequencies of interest.
According to an embodiment of the present invention, a data shuffler apparatus performs data shuffling of input bits to effect the dynamic element matching mentioned above. The data shuffler apparatus includes N input shufflers, each input shuffler having N input terminals and N output terminals, where N>2, each input terminal of each input shuffler receiving a respective one of the input bits. The shuffler apparatus also includes N output shufflers, each output shuffler having N input terminals and N output terminals, the input and output shufflers being interconnected such that each of the N output terminals of each input shuffler is connected to a respective input terminal of a different one of the N output shufflers (that is, each of the N output terminals of each input shuffler is connected to a respective input terminal of a different member of the set of N output shufflers). Each input and output shuffler is configured to output shuffled bits at its output terminals based on the input bits received at its input terminals, so as to balance (that is, equalize) the number of high-level logic bits outputted from each of the output terminals over time. In an embodiment, all of the shufflers operate in a substantially identical manner to each other.
Further embodiments of the present invention are described below.
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Broadcom Corporation
Nguyen John B
Sterne Kessler Goldstein & Fox P.L.L.C.
Young Brian
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