Shrinking key generator for parallel process

Cryptography – Key management – Having particular key generator

Reexamination Certificate

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C380S043000

Reexamination Certificate

active

07742598

ABSTRACT:
A parallel processing shrinking key generator is provided. The parallel processing shrinking key generator includes: a selection linear feedback shift register (LFSR); a source LFSR; a selection logic circuit for selecting one of a source bit of the source LFSR and a predetermined input bit according to a selection bit of the selection LFSR; an index counter for assigning an index where output bits of the selection logic circuit are stored at a next clocking of a clock signal; and an output amount register for shifting an output bit of the selection logic circuit according to the assignment of the index counter.

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D. Coppersmith et al., “The Shrinking Generator,” Springer-Verlag, 1998, pp. 22-39.
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Don Coppersmith, et al.; “The Shrinking Generator”; Springer-Verlag; 1998; pp. 22-39.

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