Shrinkable BiCMOS circuit layout

Details Shrinkable BiCMOS circuit layout Shrinkable BiCMOS circuit layout

1992-06-01

1995-12-19

Trans, Vincent N.

Boots, shoes, and leggings

364491, G01F 1750

Patent

active

054774675

ABSTRACT:
A BiCMOS integrated circuit design having an oversized isolation area surrounding circuit elements which are non-scaleable is provided. The non-scaleable circuit elements can be removed from the layout, and the remaining scaleable elements shrunk by a CAD system. After shrinking the scaleable elements and the isolation area, the non-scaleable elements are returned to the layout at their original size, and located within the scaled-down isolation area.

REFERENCES:
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 4897703 (1990-01-01), Spratt et al.
patent: 4912055 (1990-03-01), Min et al.
patent: 4985744 (1991-01-01), Spratt et al.
patent: 5119314 (1992-06-01), Hotta et al.
patent: 5231590 (1993-07-01), Kumar et al.
"Introduction to MOS LSI Design" by J. Mavor et al., Addison-Wesley Publishing Company, 1983, pp. 2, 7-8 and 81-85.
"Automatic Sizing of Power/Ground (P/G) Networks in VLSI" by Dutta et al., IEEE/ACM 26th Design Automation Conference, 1989, pp. 783-786.

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