Boots – shoes – and leggings
Patent
1991-06-21
1994-03-29
Trans, Vincent N.
Boots, shoes, and leggings
364490, 364489, 364488, G06F 1560
Patent
active
052991393
ABSTRACT:
An improved circuit layout-verifying system and method operates on a plurality of polygons that are representative of an electrical node to test the proper or improper connection of each polygon to another contiguous polygon and designates for display those polygons that represent improper connections between known or identified reference points on the node. Traversals along a sequence of contiguous polygons between known reference points on the same electrical node are designated as proper connections or successes, and traversals along a sequence of contiguous polygon between reference points associated with different electrical nodes are designated as improper connections or failures at least along a portion of the sequence. Data from all traversals of all polygons from all known reference points is then analyzed to remove unambiguous sequences of polygons for the improperly connected electrical nodes. High resolution analysis is performed on large, single electrical nodes by selectively breaking down the node into subpolygons that can be analyzed in the previous manner.
REFERENCES:
patent: 3617714 (1971-11-01), Kernighan
patent: 4651284 (1987-03-01), Watanabe et al.
patent: 5062054 (1991-10-01), Kawakami et al.
"Programs for Verifying Circuit Connectivity of MOS/LSI Mask Artwork" by Takashima et al; IEEE 19th Design Automation Conf., 1982, pp. 544-550.
"EXCL: A Circuit Extractor for IC Designs" by McCormick, IEEE 21st Design Automation Conf., 1984, pp.616-623.
Baisuck Allen
Hoover, III William W.
Cadence Design Systems Inc.
Fernandez Dennis S.
Kaslow Kenneth M.
Trans Vincent N.
Truong Phong K.
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