Short circuit reduced CMOS buffer circuit

Details Short circuit reduced CMOS buffer circuit Short circuit reduced CMOS buffer circuit

1997-05-16

1999-07-27

Callahan, Tim

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327391, 327437, 326 27, H03K 1716, H03K 17687

Patent

active

059296801

ABSTRACT:
In this invention is described a CMOS buffer that reduces short circuit current in the output stage. The short circuit current is a result of current flowing between circuit bias and ground through the output transistors during switching transition. The reduction in shorting current is accomplished by driving the two CMOS output transistors of opposite type separately, and providing a turn off signal for one output transistor ahead of the turn on signal for the other transistor. Thus one transistor is turned off before the other transistor is turned on, reducing shorting between the two transistors. The on and off signal delay is controlled from unbalanced inverters connected separately to each input of the output transistors.

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