Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-08-23
2003-02-18
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S537000
Reexamination Certificate
active
06522159
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to short-circuit failure analyzing method and apparatus for specifying a position where a short-circuit failure occurs in an integrated circuit such as LSI, VLSI, or the like and, more particularly, to short-circuit failure analyzing method and apparatus which can process a failure analysis at a high speed even in a large scale integrated circuit.
2. Description of the Related Arts
Hitherto, an analysis of a failure in an integrated circuit determined as a defective device is performed mainly on the basis of a result of a function test and a failure simulation. In the conventional failure analysis, however, since it is performed on the assumption of a fixed failure of 0/1, in many cases, a failure analysis to specify a failure position cannot be performed with respect to the short-circuit failure in a wiring or a transistor.
On the other hand, in a CMOS LSI, generally, although a power source/current hardly flows in a state where an internal circuit is not operated, if there is a short-circuit failure, a fail current flows between a power source and the ground. There is a quiescent power source current test (Iddq test) to analyze the short-circuit failure by using such a nature. According to the failure analysis by the quiescent power source current test, failure positions are narrowed down to hundreds of gates or less by another means and, after that, they are analyzed. According to the failure analysis by the quiescent power source current test, however, when the number of gates is increased, the number of nets is also increased enormously. The failure analysis requires a long time and, in addition, when the scale is enlarged, the analysis cannot be performed.
SUMMARY OF THE INVENTION
According to the invention, there are provided short-circuit failure analyzing method and apparatus which can analyze even a large scale integrated circuit having millions of gates or more and can analyze it at a high speed.
A short-circuit failure analyzing method of the invention has a procedure comprising: a measurement pattern forming step; an internal state value deriving step; a testing step; a variable forming step; and a discriminating step. In the measurement pattern forming step, a setting of an internal logical state of an integrated circuit is changed and a plurality of measurement patterns to be used for a quiescent power source current test (Iddq test) are formed. In the internal state value deriving step, an internal state value 0/1 for each net at the time when the measurement pattern is supplied due to a simulation of the integrated circuit is derived. In the testing step, a plurality of measurement patterns are supplied to the integrated circuit determined as a defective device, a quiescent power source current (Iddq) is measured, and a pass or fail test result is obtained for each measurement pattern. In the variable forming step, on the basis of the measurement patterns, and the internal state value and test result of each net, a state value variable (netdata_n) in which the internal state values of all of the measurement patterns have been stored every net (net number n) and a test result variable (passdata) in which the pass or fail test result has been stored every measurement pattern are formed. In the discriminating step, the state value variable (netdata_n) and the test result variable (passdata) for each net are compared, thereby discriminating a combination of the short-circuited nets in the integrated circuit as a failure position. As mentioned above, according to the invention, the logical state values in all of the measurement patterns of each net due to the simulation are substituted into one state value variable (netdata_n) on a net unit basis, results of the quiescent power source current tests of all of the nets in all of the measurement patterns are substituted into another test result variable (passdata), a combination test result variable (passdata) of the internal state value variable (netdata_n) of each net is combined, and resultant variables are compared between the nets, so that the short-circuit failure position can be specified. In the comparison of the combined variables, since it is sufficient to mutually compare them among all of the nets, when the number of nets is assumed to be (n), they are compared by a league match system (round robin system). In principle, the number of times of comparison is equal to up to (n
2
−n)/2. Accordingly, even a large scale integrated circuit having millions of gates or more can be analyzed at a high speed.
The discriminating step includes a pass pattern comparing step and a fail pattern comparing step. In the pass pattern comparing step, a pass pattern (pass pattern P_n) of each net is obtained as a combination of the variables by the AND of the state value variable (netdata_n) and the test result variable (passdata) of each net. It is presumed that the short-circuit position exists between the nets whose pass patterns have the same logical value (P_A=P_B).
In the pass pattern, although a fail current does not flow in the quiescent power source current test, this is because the short-circuited nets have the same logical value. Therefore, the short-circuit failure exists between the nets having the same logical value in the pass pattern.
In the fail pattern comparing step, with respect to each net in which the existence of the short-circuit failure has been presumed in the pass pattern comparing step, a first fail pattern (F_A) of each net is obtained by the AND of the state value variable (netdata_n) of the net and an inverted value ({overscore ( )}passdata) of the test result variable, a second fail pattern (F_B) of each net is obtained by the AND of an inverted value ({overscore ( )}netdata_n) of the state value variable of each net and the inverted value ({overscore ( )}passdata) of the test result variable, it is presumed that a short-circuit position exists between two nets in which their first fail patterns and the second fail patterns of the two nets mutually have the same logical value (F_A=F_B), and a presumption result is outputted. In the fail pattern, although a fail current flows in the quiescent power source current test, this is because the mutual short-circuited nets have the opposite logical values. Therefore, a short-circuit failure exists between the nets in which parts or the whole portions in the fail pattern have the opposite logical values. That is, the short-circuit failure exists between the two nets in which the first fail pattern and the second fail pattern are the same.
In the variable forming step, the state value variables having the same value of a plurality of nets are collected into one group. In this case, in the discriminating step, one of the state value variables of an arbitrary representative net is selected from the grouped variables and a short-circuit failure is discriminated. In this manner, by grouping the same state value variables, the number of combination variables to be used for comparison can be reduced to a value smaller than the number of nets and the processing speed can be raised. In the variable forming step, when an unsteady state X or a high impedance state Z is included in the internal state of each net, in addition to the state value variable (netdata_n) of each net, a mask variable (maskdata_n) in which the logical value “1” has been stored in the fixed state of the state value variable and the logical value “0” has been stored in the unsteady state X or high impedance state Z is formed. In this case, in the discriminating step, combinations of the state value variable (netdata_n) of each net, mask variable (maskdata_n) of each net, and test result variable (passdata) are compared, thereby determining the short-circuit position in the integrated circuit. Also in this case, the comparison discriminating step has a pass pattern comparing step and a fail pattern comparing step. In the pass pattern comparing step, a pass pattern (passpattern P_n) for each n
Fujitsu Limited
Karlsen Ernest
Staas & Halsey , LLP
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