Short-circuit current-limit circuit

Details Short-circuit current-limit circuit Short-circuit current-limit circuit

2000-05-08

2001-09-04

Patel, Rajnikant B. (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C327S437000, C361S087000

Reexamination Certificate

active

06285177

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to circuits and more particularly to a current-limit circuit.
BACKGROUND ART
A short circuit condition in an electrical device can cause an excessive amount of current to be drawn through a power transistor, which may potentially damage the power transistor and other electrical components of the device. Therefore, many electrical devices include a current-limit circuit to limit the amount of current drawn though the power transistor in the event of a short circuit condition. Known current-limit circuits utilize various techniques to provide current limiting protection. Due to the extensive prior use of bipolar transistors, many conventional current-limit circuits are designed for bipolar circuits, which may not be suitable for metal oxide semiconductor (MOS) circuits.
U.S. Pat. No. 4,612,497 to Ulmer describes a current-limit circuit that utilizes MOS technology. The current-limit circuit of Ulmer includes a P-channel metal oxide semiconductor (PMOS) driver transistor. The source of the driver transistor is connected to a supply voltage, while the drain of the driver transistor is coupled to a current mirror. The current mirror is formed of a pair of PMOS transistors. The sources of the current mirror transistors are coupled to the driver transistor. The drain of the first current mirror transistor is connected to an output terminal, while the drain of the second current mirror transistor is connected to electrical ground via a current sink transistor. The drain of the second mirror transistor is also connected to the gates of the first and second mirror transistors. The first current mirror transistor is a power device and is significantly larger than the second current mirror transistor and the current sink transistor. During normal operating conditions, the first mirror current transistor operates in a non-saturated region and the amount of current sourced by the first mirror current transistor to the output terminal is not limited. However, when the first mirror current transistor becomes saturated by increased supply of current beyond a threshold value, the current sourced by the first current mirror transistor is limited, due to the current mirror effect.
A concern with the current-limit circuit of Ulmer is that current is consistently drawn through the second current mirror transistor and the current sink transistor, even during normal operating conditions. Thus current-limit circuit of Ulmer is implemented in a portable electrical device, power dissipation may become an issue.
Although known current-limit circuits, including the current-limit circuit of Ulmer, operate well for their intended purpose, what is needed is a current-limit circuit that provides short-circuit protection without significant power dissipation during normal operating conditions.
SUMMARY OF THE INVENTION
A current-limit circuit and a method of limiting current supplied to a load through a power transistor utilize a control transistor that is selectively activated to a conducting state to limit the current conducted through the power transistor in response to a predefined condition. The predefined condition may be a short-circuit condition or an over-current condition. The configuration and operation of the control transistor are such that, when the control transistor is in a conducting state, the current conducted through the power transistor is limited by the structural ratio of the two transistors. However, during normal operating conditions when the control transistor is deactivated to a non-conducting state, the control transistor does not degrade the performance of the power transistor.
In a first embodiment, the current-limit circuit is configured to provide protection from a short-circuit condition. In this embodiment, the current-limit circuit includes the power transistor, the control transistor, a current source and a switching transistor. Each of these transistors is an N-channel metal oxide semiconductor (NMOS) transistor. The power transistor is configured as a source follower between a supply voltage (V
DD
) rail and an output terminal. The gates of the power and control transistors are coupled to each other and to the current source. The current source is configured to receive a high voltage current from an external source, such as a charge pump. The switching transistor is connected between the control transistor and the output terminal. The gate of the switching transistor is supplied with V
DD
.
Under normal operating conditions, both the control and switching transistors are deactivated to a non-conducting state. However, when a short-circuit condition occurs, the switching transistor is automatically activated to a conducting state, since the voltage on the output terminal is driven to zero or near zero. The activation of the switching transistor also activates the control transistor to a conducting state. Due to the electrical arrangement of the control transistor and the power transistor, the amount of current conducted through the power transistor is then limited by the structural ratio of these transistors.
In a second embodiment, the current-limit circuit is configured to provide protection from an over-current condition, in addition to protection from a short-circuit condition. In this embodiment, the current-limit circuit further includes a resistor and a sense transistor that are connected in series between the V
DD
rail and the output terminal. The sense transistor is gate coupled to the power transistor. The current-limit circuit of the second embodiment also includes an over-current control device and a switch. The over-current control device is connected to a node between the resistor and the sense transistor to sense the voltage at the node. The voltage at the node varies in accordance with the amount of current being conducted through the power transistor. Thus, by sensing the voltage at the node, the over-current control device can detect when the current conducted through the power transistor exceeds a prescribed threshold current level. The over-current control device is also connected to the switch that can provide a conduction path from the control transistor to the output terminal when the switch is closed.
Under normal operating conditions, the switch is open. Thus, the control transistor is deactivated to a non-conducting state. However, when the current conducted through the power transistor exceeds the threshold current level, the over-current control device sends a close signal to the switch to connect the control transistor to the output terminal. When the control transistor is connected to the output terminal, the control transistor is activated to a conducting state, which limits the current being conducted through the power transistor to a lower level.
In a preferred embodiment, the sense transistor and the power transistor are structurally integrated into a single semiconductor device. The integrated device is a honeycomb structure that is composed of a number of adjacent cell blocks. Each cell block of the integrated device includes a number of source, main drain and dummy drain cells. These cells are positioned in an alternating fashion such that an adjacent cell of a source cell is either a main drain cell or a dummy drain cell. Each cell block also includes a body contact region that is positioned around the cells. Thus, the body contact region is located in the periphery of a cell block.
The electrical connections to the cells and the body contact regions of the cell blocks are provided by M
1
metallizations and M
2
metallizations. The M
1
metallizations are formed of a first layer of metal positioned over the cells and the body contact regions, while the M
2
metallizations are formed of a second layer of metal positioned over the M
1
metallizations. For each cell block, the main drain cells are connected to M
1
main drain metallizations, while the dummy drain cells are connected to at least one M
1
dummy drain metallization. The M
2
metallizations that overlay the M
1
metallizations

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