Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-08-05
2003-07-22
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S777000
Reexamination Certificate
active
06597062
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to high input/output (I/O), high density, low cost electronic modules and, more particularly, to high I/O, high density, low cost packaging of high performance, high density memory devices such as RAMBUS® devices using impedance-controlled buses for maintaining high electrical performance.
BACKGROUND OF THE INVENTION
In data processing and network systems, it is always a certainty that the demand in memory throughput will increase at a high rate. In recent years such increase has taken on a new dimension. While the demand for memory throughput has increased, the space available for mounted memory devices has become increasingly restricted.
RAMBUS architecture-based memory devices are the fastest commercially available memory devices, operating at frequencies up to 533 megahertz. A 16-bit RAMBUS data bus has an effective maximum throughput of 2.1 gigabytes per second (GB/s). In comparison, the maximum throughput available from a 64-bit Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) data bus using the fastest DDR memory devices available is only 2.7 GB/s. Therefore, the effective throughput of a 64-bit RAMBUS data bus, implemented by using four RAMBUS-ASIC Cells (RACs) is 8.4 GB/s, or more than three times the throughput of an equivalent DDR SDRAM based system.
The RAMBUS architecture achieves this performance by serially connecting memory devices on a bus rather than using the more common parallel connecting, as found in SDRAM based memory subsystems. To ensure fast memory cycle times, extremely short, fast rise pulses are used. The RAMBUS architecture also makes use of separate differential clock pairs for data in both the transmit and receive directions to improve the bus efficiency and operational speeds. Parceling clocks and data together and minimizing skew between data/clocks and control information within a given packet make it possible to have multiple data packets co-existing on the channel boosting the overall performance and operational speed of the architecture.
A RAMBUS channel supports from one to 32 memory devices, making for a very granular architecture. The memory devices can either be mounted on a system board or located on modules that are then inserted into the system board. Currently, RAMBUS technology features a memory configuration wherein memory devices are disposed (packaged) on up to three RAMBUS Inline Memory Modules (RIMMs) or small outline RIMMs (SO-RIMMs) all interconnected on a system board by a high speed data bus. One or more termination components are placed on the system board at the physical end of the bus.
It is critical that the RAMBUS channel is uniform and capable of achieving the low intra-packet skew variations and voltage margins requirements within the operational speeds to be supported. RIMM and SO-RIMM memory modules and mating sockets have difficulty in achieving this, especially as operating frequencies continue to increase.
Memory subsystems based on the RAMBUS architecture offer space-saving advantages over alternative memory architectures such as DDR SDRAM for an equivalent level of data throughput. For example, there are many high data rate, space-constrained applications where there is only enough space available for a single memory device on a channel. In such application, a single RAMBUS device placed adjacent to the host chip typically offers three times the throughput of a single device DDR SDRAM channel and six times the throughput of a single device SDRAM memory subsystem.
Many SDRAM and DDR SDRAM memory subsystems will be further space-constrained to provide for a certain minimum defined bus width within their respective architectures. This often means that the memory subsystem will contain a minimum of four or eight memory devices since the alternative of using 32-bit or 64-bit memory devices is usually not an acceptable option due to cost or availability. Also, the memory devices in the RAMBUS architecture are serially connected to the bus, making it possible to locate the memory devices closer to the host chip and therefore saving space. In a DDR SDRAM-based memory subsystem, this is not possible due to the requirement of length matching on the data bus.
The inclusion of bus terminations on the memory modules themselves also provides several types of performance improvement. First, because only a single set of contacts need be used (i.e., there is no need to have the bus lines exit the module), the additional contact capacity may be devoted to addressing an additional channel of memory on the same module. This also significantly reduces the total bus path length since the portion of the bus path between the memory modules and the external terminator resistors of the prior art is eliminated. In a stacked memory subsystem, the terminations may be provided on a separate termination module with little degradation in performance or increase in required space.
Traditionally, a piece of rack-mountable equipment has a standard width of 19 inches and a height in increments of 1.75 inches. This is also known as “1U.” However, a trend has begun to reduce the height for the servers in a server rack to dimensions appreciably lower than 1U. This equipment height restriction has also placed height restrictions on other components such as memory modules. Traditional RIMMs are simply too tall to be able to be mounted vertically on the system board.
There are applications where each processor requires two or more short channels of memory. If standard RIMMs or SO-RIMMs are used, a significant amount of printed circuit board space is wasted and additional printed circuit trace length is required. Furthermore, RIMMs and SO-RIMMs do not have the quantity of I/O or connections necessary to support more than two channels of memory, even if the modules are self-terminated. A solution is needed to meet the requirements for higher I/O, reduced printed circuit board real estate, and shorter printed circuit trace lengths.
It is desirable to find a packaging solution resolving both the throughput and the density issues. In addition, the solution must also be low in cost, readily manufacturable, upgradeable with ample granularity, have improved electrical performance even at high frequencies, and have good reliability. Ample granularity allows the amount of memory on a given memory module to be increased or decreased in smaller increments (e.g., in increments of 64 megabytes, instead of 128 megabytes).
It is therefore an object of the invention to provide a high throughput, high density, low profile RAMBUS memory module for high performance memory devices.
It is another object of the invention to provide a high throughput, high density, low profile RAMBUS memory module that is readily manufacturable and upgradable.
It is still another object of the invention to provide a high throughput, high density, low profile RAMBUS memory module providing improved electrical performance at high frequencies and good reliability.
SUMMARY OF THE INVENTION
The present invention is a family of specialized embodiments of the modules taught in the referenced copending U.S. patent applications. A memory module is desired with granularity, upgradeability, and high throughput of at least 4.2 gigabytes per second using two channels of RAMBUS memory devices in a typical volume of just 2.2 inches by 1.1 inches by 0.39 inch.
Each module includes a substrate having contact pads and memory devices on its surfaces, and impedance-controlled transmission line signal paths to support high speed operation. The substrates may be conventional printed circuit cards, preferably with packaged memory devices along with other components attached directly to both sides of the substrates.
The inclusion of spaced, multiple area array interconnections allows a row of memory devices to be serially mounted between each of the area array interconnections, thereby minimizing the interconnect lengths and facilitating matching of interconnect lengths. The footprints for the interconnections between the substrates and
Li Che-yu
Moriarty Sharon L.
High Connection Density Inc.
Ho Tu-Tu
Salzman & Levy
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