Short channel IGFET process

Details Short channel IGFET process Short channel IGFET process

1989-12-10

1991-02-12

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437162, 437193, 437980, 148DIG19, 148DIG26, 357 233, H01L 21336

Patent

active

049923889

ABSTRACT:
A process is disclosed for the fabrication of semiconductor devices which yields a device having a very short effective channel length and having polycrystalline source and drain electrodes. In accordance with the disclosed process, a semiconductor substrate is provided having a masking element positioned on the substrate surface. A layer of polycrystalline silicon is deposited on the exposed areas of the substrate surface by the process of selective deposition. The selectively deposited polycrystalline silicon is doped with conductivity determining impurities and that impurity material is thereafter redistributed to dope the underlying substrate to form source and drain regions. The masking element is removed to expose the portion of the semiconductor surface between the source and drain regions and to allow for a subsequent optional channel implantation. A gate insulator is formed overlying that portion between the source and drain regions and a second layer of silicon is deposited to overlay the gate insulator. The second layer of silicon is patterned to form the gate electrode of the insulated gate field effect transistor.

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Terman, L. M., IBM Technical Disclosure Bulletin, vol. 13, No. 11, Apr. 1971, pp. 3279-3280.
Furumura, Y. et al., "Selective Growth of Polysilicon", J. Electrochem. Soc., vol. 133, No. 2, Feb. 1986, pp. 379-383.

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