Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
1999-12-17
2001-07-17
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S271000, C327S278000
Reexamination Certificate
active
06262618
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an integrated circuit gate driver for driving MOSgated power devices used in motor controller and other applications and, more specifically, to a novel driver IC for a motor controllers application which prevents the simultaneous turn on of high side and low side MOSgated devices.
2. Description of the Related Art
Gate driver integrated circuits for control of MOSgated power devices, such as from MOSFETs, IGBTs, gate controlled thyristors and the like are well known. It is also known that in circuits using high-side and low side MOSgated devices, such as motor controllers, that the two MOSgated devices cannot be on at the same time, which would create a direct short circuit or “shoot-through” condition.
Many circuits are known to prevent this shoot-through condition. However, these circuits are complex; are not easily adjusted by a customer or for a particular application; have a relatively large power dissipation and are not accurate.
It would be desirable to produce a shoot-through prevention circuit which is simple, has smaller power dissipation and can be accurately and easily programmed by a user.
SUMMARY OF THE INVENTION
In accordance with the time delay circuit of the present invention, a four transistor comparator circuit is employed with an input voltage reference transistor and output current reference transistor, and with a single capacitor determining the total time delay between the turn on of one of the output power devices and the turn off of the other. The time delay is closely related to the capacitance value (within 10%); power dissipation is minimized; the circuit is reduced to six transistors, and the time delay (or “dead time”) can be accurately and easily programmed by the user.
More specifically the time delay circuit of the present invention includes an input terminal connected to the gate of a control transistor for controlling the state of the transistor, a timing capacitor connected in parallel across the control transistor, a current reference connected to the timing capacitor for charging the capacitor in accordance with the state of the control transistor, a voltage reference, and a comparator connected to the timing capacitor and to the voltage reference for comparing the voltage on the timing capacitor with the voltage of the voltage reference and outputting a signal to an output terminal in accordance therewith.
The circuit of the present invention is preferably formed in an integrated circuit, with the timing capacitor being internal to the integrated circuit. The voltage reference is generated by flowing current from the current reference through a resistor, the resistor preferably being disposed externally to the integrated circuit. The time delay can advantageously be programmed by adjusting the value of the external resistor.
Other features and advantages of the present invention will become apprarent when the following description of the invention is read in conjuction with the accompanying drawings.
REFERENCES:
patent: 3753012 (1973-08-01), Frederiksen et al.
patent: 4843265 (1989-06-01), Jiang
patent: 5311071 (1994-05-01), Ueda
patent: 5936451 (1999-08-01), Phillips
patent: 6091286 (2000-07-01), Blauschild
Cox Cassandra
International Rectifier Corporation
Ostrolenk Faber Gerb & Soffen, LLP
Tran Toan
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