Shift register with reduced number of components

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307224C, 307269, 307279, G11C 1928, H03K 1760

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active

041017900

ABSTRACT:
A shift register which comprises a master section including first and second P-channel MOS transistors and first and second N-channel MOS transistors, and a slave section including third and fourth P-channel MOS transistors and third and fourth N-channel MOS transistors. The junction between the drain electrode of the first P-channel MOS transistor and the source electrode of the second P-channel MOS transistor and the junction between the source electrode of the first N-channel MOS transistor and the drain electrode of the second N-channel MOS transistor are connected to an output of the master section of the preceding stage through a P-channel MOS transistor and an N-channel MOS transistor, respectively. The junction between the drain electrode of the third P-channel MOS transistor and the source electrode of the fourth P-channel MOS transistor and the junction between the source electrode of the third N-channel MOS transistor and the drain electrode of the fourth N-channel MOS transistor are connected to an output of the slave section of the preceding stage through a P-channel MOS transistor and an N-channel MOS transistor, respectively.

REFERENCES:
patent: 3578984 (1971-05-01), Ryley
patent: 3766408 (1973-10-01), Suzuki et al.
patent: 3930169 (1975-12-01), Kuhn, Jr.
patent: 4002926 (1977-01-01), Moyer
Suzuki et al., "Clocked CMOS Calculator Circuitry"; IEEE Journ. of Solid-State Circuits; vol. SC-8, No. 6, pp. 462-469; 12/1973.

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