Shift register programming for a programmable logic device

Details Shift register programming for a programmable logic device Shift register programming for a programmable logic device

1988-12-30

1990-05-29

Malzahn, David H.

Boots, shoes, and leggings

307465, H03K 14177

Patent

active

049300989

ABSTRACT:
A programmable logic device in which memory cells are removed from the signal path. Input signals are coupled to an inverting and a non-inverting buffer to provide a complementary pair of outputs from the buffers. In one embodiment, a memory cell is provided to control enablement of each buffer and the output of each pair of complementary buffers is coupled together to provide an output. In another embodiment, the complementary pair of outputs from the buffer are inputted to a multiplexer wherein a single memory cell controls the selection of the signal or its complement to be outputted from the multiplexer. The memory cells are each coupled to its corresponding latch or shift register for latching a stored state of the memory cell. Shift registers provide for external programming to emulate stored memory cell states.

REFERENCES:
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4684830 (1987-08-01), Tsui et al.
patent: 4761768 (1988-08-01), Turner et al.
patent: 4763020 (1988-08-01), Takata et al.
patent: 4774421 (1988-09-01), Hartmann et al.

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