Shift register having low power consumption and method of...

Electrical pulse counters – pulse dividers – or shift registers: c – Shift register

Reexamination Certificate

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C377S070000, C377S073000, C377S077000

Reexamination Certificate

active

11339647

ABSTRACT:
The shift register, which is an n-th shift register of a shift register chain, includes a first multiplexer, a second multiplexer, and a latch block, wherein n is a positive integer. The first multiplexer selects one of output data of the (n−1)-th shift register or output data of the (n+1)-th shift register and outputs the selected data to be used as a reset signal in the latch block. The second multiplexer selects one of the output data of the (n−1)-th shift register or the output data of the (n+1)-th shift register and outputs the selected data to be used as input data of the latch block. The latch block stores the output data of the second multiplexer in response to the clock control signal, the inverted clock control signal and the reset voltage, and outputs the stored data.

REFERENCES:
patent: RE35254 (1996-05-01), Chaisemartin et al.
patent: 6556647 (2003-04-01), Neravetla
patent: 6654439 (2003-11-01), Kommrusch
patent: 7181662 (2007-02-01), Chien
patent: 2001-135093 (2001-05-01), None
patent: 2004-185787 (2004-07-01), None
patent: 10-2004-0061958 (2004-07-01), None

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