Shift register circuit

Details Shift register circuit Shift register circuit

1986-07-16

1988-04-26

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

377105, 307481, G11C 1140, G11C 1928

Patent

active

047410035

ABSTRACT:
A shift register circuit, including a plurality of stages capable of preserving data bits entered from an external source and shifting the data bits from stage to stage, each of the stages being driven by phase one, phase two and phase three clock signals, each signal alternating between a first and a second logic level. The shift register circuit comprises a first transistor responsive to the phase one clock signal for transferring a new data bit of either first or second logic level, a series combination of second, third, fourth and fifth transistors, and an output node provided between the third and fourth transistors. The second and third transistors are responsive to the new data bit transferred through the first transistor and the phase two clock signal, respectively, to place the phase three clock signal with the logic level corresponding to that of the new data bit at the output node. The fourth and fifth transistors are responsive to a previous data bit transferred to the subsequent stage and the phase three clock signal, respectively, for canceling the logic level of the previous data bit at the output node. This circuit structure results in a reduction in power dissipation.

REFERENCES:
patent: 3794856 (1974-02-01), Baker
patent: 4295055 (1981-10-01), Takemoto et al.

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