Shift register arrays

Electrical pulse counters – pulse dividers – or shift registers: c – Shift register

Reexamination Certificate

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Details

C068S069000

Reexamination Certificate

active

07734003

ABSTRACT:
A shift register array is provided. The shift register array includes a plurality of shift registers connected in serial. The shift register includes a first transistor coupled between a first input terminal and a first node, a second transistor coupled between a first clock input terminal and an output terminal and a pull-up unit. The first transistor has a gate coupled to the first input terminal. The second transistor has a gate coupled to the first node. The pull-up unit includes a third transistor coupled between the first node and a ground, a capacitor coupled between the first clock input terminal and the second node and a fourth transistor coupled between the second node and the ground. The third transistor has a gate coupled to a second node. The fourth transistor has a gate coupled to the first node.

REFERENCES:
patent: 6970530 (2005-11-01), Wang et al.
patent: 7436923 (2008-10-01), Tobita
patent: 2006/0274021 (2006-12-01), Park et al.
patent: 2008/0012818 (2008-01-01), Lee et al.
patent: 2008/0080661 (2008-04-01), Tobita
patent: 2008/0101529 (2008-05-01), Tobita
patent: 2008/0253499 (2008-10-01), Chan et al.
patent: 1953101 (2007-04-01), None
patent: 101114525 (2008-01-01), None
English Abstract of CN101114525.
English Abstract of CN1953101.
“MOS Capacitor Pull-Up Circuits for High-Speed Dynamic Logic” Joseph P. Ellul et al.; IEEE Journal of Solid-State Circuits, vol. SC-10, No. 5, Oct. 1975.
English Abstract of CN101114525; publication dated Jan. 3, 2008.
English of CN1953101; publication date: Apr. 25, 2007.

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