Shift register and display device using same

Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix

Reexamination Certificate

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C377S072000, C377S075000

Reexamination Certificate

active

07133017

ABSTRACT:
A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

REFERENCES:
patent: 5526390 (1996-06-01), Fucili
patent: 9578440 (2000-05-01), Washio et al.
patent: 9703918 (2000-11-01), Washio et al.
patent: 6469647 (2002-10-01), Kinugasa et al.
patent: 2001-135093 (2001-05-01), None
Korean Notice of Rejection and English translation thereof mailed Jun. 27, 2005 in corresponding Korean application No. 10-2003-18577.

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