Shift register and display device

Details Shift register and display device Shift register and display device

2007-10-16

2007-10-16

Shalwala, Bipin (Department: 2629)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S096000, C345S098000, C345S099000, C345S102000

Reexamination Certificate

active

10780748

ABSTRACT:
A shift register includes unit circuits cascade-connected to form a plurality of shift stages. Each of the unit circuits has a time-shifter including a NAND circuit to receive an input pulse as one input, and a holder having a PMOS transistor and a NMOS transistor, connected in series between a power supply and a clock input of which gates and drains are mutually connected in common respectively. The input of the holder is connected to the output of the NAND circuit, and the output thereof is fed as another input to the NAND circuit. The odd-stage unit circuits and the even-stage unit circuits operate in synchronism respectively with clock pulses having a¼phase difference from each other. In this structure, the number of transistors between the positive and negative power supplies can be reduced for lowering the required supply voltage and accelerating the shift register operation.

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