Shift register

Details Shift register Shift register

2006-06-26

2008-07-08

Lam, Tuan T (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

C377S068000, C377S069000

Reexamination Certificate

active

07397885

ABSTRACT:
A shift register minimizing bias stress applied to transistors is disclosed. A shift register including n stages outputting scan pluses that are sequentially delayed in a forward or reverse direction thereof, where n is positive integer and wherein each stage includes: a scan direction controller that provides a first or second voltage to a scan direction control node according to a first or second enable signal and controlling the forward or reverse direction output; a first node controller that controls a first node according to a voltage on the scan direction control node; a second node controller that controls a second node according to the voltage on the scan direction control node and a voltage on the first node; an output unit that outputs a clock signal as scan pulse according to voltages on the first and second nodes; a third node controller that provides one of the first and second voltages to a third node according to the first and second enable signals; a first discharge circuit unit that discharges the voltage on the first node according to voltages of the second and third nodes; and a second discharge circuit unit that discharges the voltage on the third node according to one of a third enable signal and a fourth enable signal.

REFERENCES:
patent: 5859630 (1999-01-01), Huq
patent: 2004/0165692 (2004-08-01), Moon et al.
patent: 2005/0156856 (2005-07-01), Jang et al.
patent: 2007/0248204 (2007-10-01), Tobita

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