Shift register

Details Shift register Shift register

2006-10-10

2006-10-10

Lam, Tuan T. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

C377S079000, C345S100000

Reexamination Certificate

active

07120221

ABSTRACT:
An output buffer in each stage of a shift register applies a first clock signal to an output line under control of a first node and a second driving voltage to the output line under control of second and third nodes. A first node controller controls the first node using a start pulse and an output signal of the next stage. A second node controller selectively applies a voltage at a fourth node and the second driving voltage to the second node under control of the first and second clock signals. A third node controller applies the voltage at the fourth node and the second driving voltage to the third node opposite to the second node. A fourth node controller controls the fourth node such that the fourth node has a voltage opposite to the first node using a voltage at the first node and the first driving voltage.

REFERENCES:
patent: 2005/0220263 (2005-10-01), Moon
patent: 2005/0264514 (2005-12-01), Kim et al.
patent: 2006/0007085 (2006-01-01), Kim et al.

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