Shift register

Details Shift register Shift register

2002-09-25

2004-07-20

Wambach, Margaret (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Shift direction control

C377S078000, C377S079000, C377S081000, C345S098000, C345S099000, C345S100000

Reexamination Certificate

active

06765980

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to a shift register; in particular, to a bidirectional shift register.
BACKGROUND OF THE INVENTION
Conventionally, a gate driver utilizing a shift register has been utilized for a panel display device utilizing liquid crystal and plasma.
Symbol
200
in
FIG. 8
indicates a panel type display device provided with panel
211
, multiple pixels
210
formed on panel
211
, gate driver
102
, and source driver
202
.
Multiple (N, in this case) gate lines
221
1
-
221
N
and multiple (M, in this case) source lines
221
1
-
222
M
are connected to gate driver
102
and source driver
202
, respectively.
Pixels
210
are arranged in the form of a matrix, and a transistor is provided in each pixel
210
. In the transistor in 1 pixel
210
, a gate terminal and a source terminal are connected to gate line
221
x
and source line
222
m
corresponding to its position (n,m) in the matrix.
Drain terminal of the transistor in each pixel is connected to an electrode used to apply a voltage to a displaying member, such as a liquid crystal or a light-emitting element, wherein the displaying member in pixel
210
becomes bright or dark as the transistor in pixel
210
becomes conductive according to the voltage applied to the source terminal of said transistor.
In said display device
200
, gate driver
102
supplies a signal to the respective gate lines in order to make the transistors in the respective pixels conductive in a time-divided manner.
The order the signal is supplied can be either in the forward direction, that is, from first gate line
221
1
toward the Nth gate line
221
N
, or in the backward direction. When the signal is supplied from gate driver
102
to gate line
221
n
, the signal which makes the transistors conductive is applied at once to the gate terminals of M pixels
210
n,1
-
210
n,M
connected to said gate line
221
n
, and the electrical connection is achieved between the drain terminals and the source terminals of M pixels
210
n,1
-
210
n,M
connected to said gate line
221
n
.
When the signal is applied to gate line
221
n
, source driver
202
applies a voltage corresponding to the display condition of M pixels
210
n,1
-
210
n,M
connected to said gate line
221
n
.
Therefore, M pixels
210
n,1
-
210
n,M
connected to gate line
221
n
become bright or dark according to the level of the voltage supplied by source driver
202
.
When the display of 1 gate line
221
n
is finished, a voltage is supplied to next gate line
221
n+1
using the same procedure.
One screen is displayed as the first through the Nth gate lines
221
1
-
221
N
are scanned in said manner.
A block diagram of a conventional internal circuit of such a gate driver
102
is shown in FIG.
6
.
Said gate driver
102
has input level conversion circuit
112
, shift register
105
, and output level conversion circuit
106
.
Output level conversion circuit
106
has multiple (N, in this case), that is, the first through the Nth, buffer circuits
116
1
-
116
N
according to the quantity N of gate lines
221
1
-
221
N
, wherein the output terminals of buffer circuits
116
1
-
116
N
are respectively connected to gate lines
221
1
-
221
N
.
Shift register
105
has multiple (N, in this case), that is, the first through the Nth, memory circuits
115
1
-
115
N
according to the quantity of buffer circuits
116
1
-
116
N
, wherein the output terminals of memory circuits
115
1
-
115
N
are respectively connected to the input terminals of buffer circuits
116
1
-
116
N
. Signals output from respective memory circuits
115
1
-
115
N
are applied with voltage conversion and supplied to gate lines
221
1
-
221
N
by buffer circuits
116
1
-
116
N
.
Because respective memory circuits
115
1
-
115
N
of said gate driver
102
have the same configuration, the detailed internal circuit of nth memory circuit
115
n
is shown in
FIG. 7
to represent them.
Each memory circuit
115
1
-
115
N
has forward transmission input terminal F, backward transmission input terminal B, and output terminal SR.
When the forward transmission input terminal and the backward transmission input terminal of nth memory circuit
115
n
are expressed as F
n
and B
n
with the suffix n, and the output terminal is expressed as SR
n
, output terminal SR
n−1
of (n−1)th memory circuit
115
n−1
of the former stage is connected to forward transmission input terminal F
n
of nth memory circuit
115
n
, output terminal SR
n+1
of (n+1)th memory circuit
115
n+1
of the latter stage is connected to backward transmission input terminal B
n
, to which signals output from memory circuits
115
n−1
and
115
n+1
of the former and the latter stages are respectively input.
Then, output terminal SR
n
of nth memory circuit
115
n
is connected to forward input terminal F
n+1
of memory circuit
115
n+1
of the latter stage and backward transmission input terminal B
n−1
of memory circuit
115
n−1
of the former stage.
Selection circuit
117
, first and second gate circuits
124
and
125
, and first and second latch circuits
118
and
119
are provided inside of respective memory circuits
115
1
-
115
N
.
Selection circuit
117
is connected to forward transmission input terminal F
n
and backward transmission input terminal B
n
. In addition, selection signal LR and inverted selection signal XLR with the opposite polarity are input to selection circuit
117
from input level conversion circuit
112
, whereby either forward transmission input terminal F
n
or backward transmission input terminal B
n
is selected, depending on the logical combination of highs and lows of selection signal LR and inverted selection signal XLR, and the selected input terminal gets connected to first gate circuit
124
of the latter stage via inverter
123
.
Clock signal CK and inverted clock signal XCK with the opposite polarity are input to first and second gate circuits
124
and
125
. First gate circuit
124
is shut off when clock signal CK is high and becomes conductive as it changes from high to low in order to transmit the signal to first latch circuit
118
of the latter stage.
First latch circuit
118
holds the signal input and outputs said signal to second latch circuit
119
of the latter stage via second gate circuit
125
.
Second gate circuit
125
becomes conductive when clock signal CK is high, and it is shut off while first gate circuit
124
is conductive.
Therefore, as soon as clock signal CK changes from low to high, and first gate circuit
124
changes from the conductive state to the shut-off state, second gate circuit
125
becomes conductive, and the output of first latch circuit
118
is input to second latch circuit
119
. As a result of said operation, a signal with the same logic as that of the high or the low signal held in first latch circuit
118
gets held in second latch circuit
119
. The signal held in second latch circuit
119
is output from output terminal SR
n
.
When clock signal CK changes from high to low as described above, the signal input from forward transmission input terminal F
n
or backward transmission input terminal B
n
is latched into first latch circuit
118
. Then, when clock signal CK changes from low to high, the signal latched into first latch circuit
118
is transferred to second latch circuit
119
for output.
Therefore, when forward transmission input terminal F
n
is selected, the signals stored in respective memory circuits
115
1
-
115
N−1
are transmitted to memory circuits
115
2
-
115
N
of the latter stage as 1 cycle of clock signal CK is completed. When the backward transmission input terminal is selected, the signals stored in respective memory circuits
115
2
-
115
N
are transmitted to memory circuits
115
1
-
115
N−1
of the former stage as 1 cycle of clock signal CK is completed.
FIG. 9
is a timing chart for explaining the signal transmitting condition when forward transmission input terminal F
n
is selected, wherein symbol t
0
indicates the time high pulse si

Affiliated with

Also associated with

Rating

Shift register does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shift register, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shift register will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3212187