Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2000-02-09
2002-07-30
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S100000, C345S099000
Reexamination Certificate
active
06426743
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of priority of Korean Patent Application No. P994372 filed on Feb. 9, 1999, which application is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a circuit for driving an active matrix type display device of, and more particularly to a shift register for driving pixel rows in a liquid crystal display.
2. Discussion of the Related Art
Generally, a conventional liquid crystal display device used in a television or a computer includes a liquid crystal matrix having liquid crystal cells arranged at intersections of data lines with select or gate lines. The select lines are horizontal lines (i.e., row lines) of the liquid crystal matrix, which are sequentially driven with a shift register.
FIG. 1
is a block diagram showing schematically the configuration of a conventional 4-phase shift register. The shift register of
FIG. 1
includes n stages
12
1
to
12
n
which are cascade-connected to each other and connected respectively to n row lines ROW
1
to ROWn through output lines
14
1
to
14
n
. In the shift register, a start pulse SP is input to the first stage
12
1
. The second to nth stages
12
2
to
12
n
each respond to an output signal g
l
to g
n−1
of a previous stage
12
1
to
12
n−1
and two of four clock signals C
1
to C
4
select the row line ROWi connected to the pixel row. Each of the stages
12
1
to
12
n
has the same circuit configuration and shifts the start pulse toward a respective output line
14
i
every period of the horizontal synchronous signal.
Referring to
FIG. 2
, there is illustrated a circuit configuration of an arbitrary stage
12
i
shown in FIG.
1
. The stage
12
i
includes a fifth NMOS transistor T
5
for applying a high logic voltage signal to the output line
14
i
and a sixth NMOS transistor T
6
for supplying a low logic voltage signal to the output line
14
i
.
If an output signal g
i−1
of a previous stage, which is used as the start pulse, goes to a high logic level in the interval t
1
as shown in
FIG. 3
, first and fourth NMOS transistors T
1
and T
4
are turned-on. Then, a voltage signal VP
1
is charged on a first node P
1
while a voltage signal VP
2
on a second node P
2
is discharged. Therefore, the fifth NMOS transistor T
5
is turned-on by the voltage VP
1
on the first node P
1
. At this time, since a first clock signal C
1
applied to the fifth NMOS transistor T
5
has a low logic level, there is developed an output signal Vout having the low logic level on the output line
14
i
. In the interval t
2
, when the output signal g
i−1
of the previous stage is inverted to a low logic level and the first clock signal C
1
has a high logic level, the first NMOS transistor T
1
is turned-off and the voltage signal VP
1
on the first node P
1
is bootstrapped by coupling with a parasitic capacitor Cgs between the gate and source electrodes of the fifth NMOS transistor T
5
. To this end, the first clock signal C
1
having a high logic level is applied to the output line
14
i
without a leakage. Next, if the first clock signal C
1
changes to a low logic level in the interval t
3
, the output signal Vout on the output line
14
i
changes to a low logic level because the fifth NMOS transistor T
5
maintains the turned-on state. Finally, in the interval t
4
when a third clock signal C
3
having a high logic level is applied to a third NMOS transistor T
3
, the third NMOS transistor T
3
is turned-on to charge a high level voltage VDD on the second node P
2
, thereby developing a high logic level on the second node P
2
. The voltage signal VP
2
charged on the second node P
2
allows the sixth NMOS transistor T
6
to be turned-on such that the voltage charged on the output line
14
i
is discharged to a ground voltage source VSS through the sixth NMOS transistor T
6
. Also, the voltage signal VP
2
charged on the second node P
2
enables the second NMOS transistor T
2
to be turned-on, thereby discharging the voltage signal VP
1
charged on the first node P
1
toward the ground voltage source VSS through the second NMOS transistor T
2
.
In
FIG. 2
, the voltage signal VP
1
on the first node P
1
is bootstrapped to a very high level in the interval t
2
causing the bootstrapping operation. However, if the absolute threshold voltage |Vth| of the first and second NMOS transistors T
1
and T
2
is low, the voltage signal VP
1
on the first node P
1
is discharged as shown in FIG.
4
. This results from a current signal on the first node P
1
leaking through each of the first and second NMOS transistors T
1
and T
2
.
FIG. 4
shows results of a simulation for the prior shift register circuit including transistors for which the absolute threshold voltage |Vth| is low. Also,
FIG. 4
shows the waveforms of an output signal Vout of the present stage
12
i
, and the voltage signals VP
1
and VP
2
on the first and second nodes P
1
and P
2
. Referring to
FIG. 4
, the voltage signal VP
1
on the first node P
1
is distorted by a current signal leaked through each of the first and second NMOS transistors T
1
and T
2
. Due to this, the output signal Vout charged on the output line
14
i
is also distorted. As a result, it provides a disadvantage in that a next stage malfunctions. Also, the voltage signal VP
2
on the second node P
2
is unstable because of a current signal leaked by the third and fourth NMOS transistors T
3
and T
4
, as shown in FIG.
4
. Due to this, the second and sixth NMOS transistors T
2
and T
6
also malfunction. Further, since the drain and gate electrodes of the first NMOS transistor T
1
are connected to each other, the output signal g
i−1
of the previous stage is dropped down by the threshold voltage Vth of the first NMOS transistor T
1
before being applied to the first node P
1
. The output signal g
i−1
of the previous stage drops down more in the case that it is defective in the liquid crystal panel. In this case, the output signal g
i−1
of the previous stage drops down more and more with each succeeding stage until the last stage. As a result, the shift register circuit does not operate.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a shift register that is capable of increasing the range of operating voltage as well as preventing a malfunction.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to achieve these and other objects of the invention, a shift register according to one aspect includes a plurality of stages which are commonly connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator; which are connected to row lines; and which are connected, in cascade, with respect to a scanning signal, for charging and discharging the row lines.
Each of the plurality of stages included in the shift register according to another aspect comprises: a pull-up transistor having a control electrode and a conduction path connected between the first clock signal line and the output terminal; a pull-down transistor having a control electrode and a conduction path connected between the low level voltage line and the output terminal; first and second transistors having conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor, and each having a control electrode, connected commonly to the second clock signal line, the first and second transistors allowing a voltage to be charged on the control electrode of the pull-up transistor; and third and fourth tra
Kim Jin Sang
Yeo Ju Cheon
Yoon Sang Young
Chang Kent
LG. Philips LCD Co. LTD
Long Aldridge & Norman LLP
Sheng Tom V.
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