Shift register

Details Shift register Shift register

2000-03-02

2002-01-15

Lam, Tuan T. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

C377S069000, C377S070000, C377S075000

Reexamination Certificate

active

06339631

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a driving circuit for an active matrix display device, and more particularly to a shift register for driving pixel rows of a liquid crystal display device.
2. Description of the Related Art
A liquid crystal display (LCD) used as a display device for a television and a computer includes a liquid crystal matrix having liquid crystal cells arranged at intersections of data lines (i.e., column lines) with selection lines (i.e., row lines). These selection lines are horizontal lines (i.e., row lines) of the liquid crystal matrix and are selected by a shift register.
As shown in
FIG. 1
, the conventional shift register includes n stages
2
1
to
2
n
that are connected in cascade and that are connected, via output lines
4
1
to
4
n−1
, to n row lines ROW
1
to ROW
n
, respectively. The first stage
2
1
receives a start pulse SP, and the second to n
th
stages
2
2
to
2
n
receive output signals g
1
to g
n−1
of the previous stages
2
1
to
2
n−1
. Also, the 1
st
to n
th
stages
2
1
to
2
n
shift the start pulse SP, or the output signals g
1
to g
n−1
of the previous stages
2
1
to
2
n−1
, respectively, by two of three clock signals C
1
to C
3
, thereby sequentially enabling row lines ROW
i
connected to the pixel rows.
As shown in
FIG. 2
, each of the stages
2
1
to
2
n
in
FIG. 1
includes a fifth NMOS transistor T
5
for applying a high logic level voltage signal to an output line
4
i
, and a sixth NMOS transistor T
6
for applying a low logic level voltage signal to the output line
4
i
. Also, each stage
2
i
includes a first NMOS transistor T
1
for receiving the start pulse SP, or an output signal g
i−1
of the previous stage
2
i−1
at gate and drain terminals thereof, and a third NMOS transistor T
3
for receiving the third clock signal C
3
at the gate terminal thereof. The third clock signal C
3
is changed from a low logic level into a high logic level simultaneously with the output signal g
i−1
, of the previous stage
2
i−1
. Accordingly, the third NMOS transistor T
3
and the fourth NMOS transistor T
4
are simultaneously turned on. Since the W/L ratio of the fourth NMOS transistor T
4
(wherein W is a channel width and L is a channel length) is larger than that of the third NMOS transistor T
3
, a voltage VP
2
at a second node P
2
has a low logic level close to the ground voltage level. As described above, the stages
2
1
to
2
n
included in the conventional shift register have a ratio logic. Since a voltage VP
1
at a first node P
1
has a voltage level close to the output signal g
i−1
of the previous stage
2
i−1
input via the first NMOS transistor T
1
, a fifth NMOS transistor T
5
is turned on. At this time, the first clock signal C
1
maintains a low logic level, so that a low logic level voltage signal appears at the output line
4
i
.
If the first clock signal C
1
changes from a low logic level to a high logic level while the voltage VP
1
at the first node P
1
remains at a high logic level, the output line
4
i
charges to the high logic level voltage of the first clock signal C
1
input via the fifth NMOS transistor T
5
. At this time, the first node P
1
is coupled to the output terminal
4
i
by a parasitic capacitor C
gs
existing between the gate terminal and the drain terminal of the fifth NMOS transistor T
5
, thereby allowing a charge voltage VP
1
at the first node P
1
to be raised to a higher level.
Accordingly, a high logic level voltage of the first clock signal C
1
is applied to the output line
4
i
without loss. The first and fourth NMOS transistors T
1
and T
4
are turned off by the output signal g
i−1
of the previous stage
2
i−1
changing from a high logic level into a low logic level. Subsequently, if the first clock signal C
1
changes from a high logic level to a low logic level again, then the fifth NMOS transistor T
5
remains a turned-on state, so that a voltage V
out
at the output line
4
i
changes to a low logic level. Next, if the third clock signal C
3
changes from a low logic level to a high logic level again, the third NMOS transistor T
3
is turned on, thereby allowing a supply voltage V
cc
to be charged onto the second node P
2
. Thus, a high logic level voltage VP
2
appears at the second node P
2
. At this time, the sixth NMOS transistor TG receiving a high logic voltage VP
2
of the second node P
2
at its gate terminal is turned on to discharge a voltage V
out
at the output line
4
i
to a ground voltage level V
ss
. Accordingly, a output voltage V
out
at the output line
4
i
has a low logic level. Likewise, the second NMOS transistor T
2
receiving a high logic level voltage VP
2
at its gate terminal also is turned on to discharge a charge voltage VP
1
at the first node P
1
onto the ground voltage level V
ss
. As a result, a charge voltage VP
1
at the first node P
1
has a low logic level. As described above, the conventional shift register sequentially shifts the start pulse SP from the first output line
4
1
to the n
th
output line
4
n
using the clock signals C
1
to C
3
, thereby sequentially driving the output lines
4
1
to
4
n
.
However, the conventional shift register needs four pulse signals including three clock signals C
1
to C
3
and a start pulse SP and, at the same time, requires a circuitry for generating the clock signals and the pulse signals. This causes a complication in the structure of the external control circuit, as well as an increase in the manufacturing cost.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a shift register that is suitable for reducing the required number of clock signals and for simplifying an external control circuit.
In order to achieve these and other objects of the invention, each stage in the shift register according to one aspect of the present invention includes an output circuit for responding to a first control signal to apply any one of the first and second clock signals to the row line of the liquid crystal cell array and thus to charge the row line, and for responding to a second control signal to discharge a voltage at the row line; and an input circuit for responding to a clock signal different from any one of an output signal of the previous stage and the start pulse to generate the first control signal, and for responding to a clock signal different from the first control signal to generate the second control signal.
A shift register according to another aspect of the present invention includes odd-numbered stages each having an output circuit for responding to a first control signal to apply the first clock signal to the odd-numbered row line of the liquid crystal cell array and for responding to a second a-control signal to discharge a voltage at the odd-numbered row line of the liquid crystal cell array; and an input circuit for responding to any one of an output signal of the previous stage and the start pulse and the second clock signal to generate the first and second control signals, and even-numbered stages each having an output circuitry for responding to a third control signal to apply the second clock signal to the even-numbered row line of the liquid crystal cell array and for responding to a fourth control signal to discharge a voltage at the even-numbered row line of the liquid crystal cell array; and an input circuit for responding to an output signal of the previous stage and the first clock signal to generate the third and fourth control signals.
A shift register according to still another aspect of the present invention includes (3k)th stages (wherein K is an integer), each having a first output circuit for responding to a first control signal to apply the first clock signal to the (3k)
th
row line of the liquid crystal cell array and for responding to a second control signal to discharge a voltage at the (3k)
th
row line of the liquid crystal cell array; and a first input circuit for responding to

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