Shift redundancy scheme for wordlines in memory circuits

Details Shift redundancy scheme for wordlines in memory circuits Shift redundancy scheme for wordlines in memory circuits

2000-06-17

2001-07-17

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S200000, C365S189110

Reexamination Certificate

active

06262935

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to circuitry for memory circuits and more particularly to control circuitry for memory circuits that performs a row redundancy function to overcome the adverse effects of defective memory cells.
BACKGROUND OF THE INVENTION
Read/write memory circuits store data by a process called writing and permit the subsequent retrieval of that data by a process called reading. In a conventional memory circuit, data is stored in a plurality of storage locations arranged as an array of memory cells. Each storage location is identified by an address, which might include both a row identifier and a column identifier. The amount of data that can be stored in the cells of a memory circuit is known as the storage capacity of the circuit. Each cell is accessed by use of decoder circuitry. Column and row decoder circuitry may be used for accessing the cells of a memory circuit. In conventional memory circuits, data lines transfer the data to the storage locations during a write cycle and transfer the data from the storage locations during a read cycle.
One specific type of memory circuit is known as a random access memory circuit (“RAM”). Random access memory circuits permit the storage locations to be accessed randomly, and further permit data to be both read from and written to the storage locations of the memory circuit. RAM circuits generally come in two forms. The first form of RAM is known as a static RAM circuit (“SRAM”). A primary characteristic of an SRAM circuit is that the circuit uses latches so that the storage locations of the circuit indefinitely retain the data stored therein, provided power is connected to the circuit. The second form of RAM is known as a dynamic RAM circuit (“DRAM”). A primary characteristic of a DRAM circuit is that the circuit uses charge storing elements, such as capacitors, to retain the stored data in the storage locations, and the circuit must periodically recharge (i.e., refresh) the data in order to retain same.
As will be appreciated by those skilled in the art, on occasion, memory cells and/or memory arrays in memory circuits have one or more defects. Such defects can be the result of a variety of sources. Some defects arise due to variations during the manufacturing processes. Others are the result of problems occurring during operation of the memory circuit.
Single cell failures can be isolated and spread throughout the memory array. Alternatively, a group of defective cells can be associated with each other. When a multi-cell failure occurs, the failure of certain ones of those cells can be characterized as a wordline (or row) failure if those defective cells share a common wordline (row) address. The multi-cell failure can be characterized as a bit line (or column) failure if those defective cells share a common bit line (column) address. Such multi-cell failures can also be characterized by both.
In many cases, memory circuits can still function properly, even when they have defective cells. Once detected, defective cells can be replaced with spare cells, provided spare cells are included in the array. Including on-chip spare cells to repair cell failures is known in the art as on-chip redundancy. A typical state of the art redundancy scheme has one or more spare rows (row redundancy) and/or one or more spare columns (column redundancy). These spare rows and/or columns have fuses and programmable control circuitry responsive to the wordline (row) address or bit line (column) address of the defective row or column. The control circuitry also inhibits selection of the defective cell. From an electrical standpoint, a memory circuit repaired by way of a redundancy scheme is identical to a memory circuit without any defective cells.
Although prior art wordline redundancy schemes are useful for certain applications, they have at least three significant problems associated therewith. First, use of control circuitry that performs prior art wordline redundancy schemes sacrifices performance of the memory circuit. In this regard, memory circuits using spare elements in lieu of main elements are typically relatively slower than memory circuits without any defective cells. In particular, the wordline (row) select lines are slower for the spare elements than they are for the main elements, generally because the repaired address gets routed through fuses or additional control circuitry.
Second, use of control circuitry that performs prior art wordline redundancy schemes results in area penalty. In particular, under prior art wordline redundancy schemes, fuses on the row decoder pitches are typically necessary to decode the row addresses of wordlines having defective memory cells and to disable those row addresses. At least one fuse is typically required for each wordline driver to selectively disable same, as desired. Because these fuses take up a relatively large space, a relatively large area is required for the memory array.
Third, and related to the second limitation of the prior art wordline redundancy schemes, use of control circuitry that performs prior art wordline redundancy schemes typically requires a relatively large fuse count. Furthermore, a relatively large amount of data indicative of information regarding each fuse must be stored, including its location and its corresponding memory address. With modem DRAMs having storage capacities in the gigabit order, it will be appreciated that a relatively large number of fuses are required for row decoder pitches, and a relatively large amount of data must be stored and readily accessible.
An object of the preferred forms of the invention is to overcome the above-recited problems of prior art wordline redundancy schemes.
Another object of the preferred forms of the invention is to provide a new and improved wordline redundancy scheme to overcome the adverse effects of defective memory cells.
Yet another object of the preferred forms of the invention is to provide a wordline redundancy scheme that shifts the addressing of wordlines around a defective or bad memory cell.
These and other objects of the preferred forms of the invention will become apparent from the following description. It will be understood, however, that an apparatus could still appropriate the invention claimed herein without accomplishing each and every one of these objects, including those gleaned from the following description. The claims, not the objects, define the subject matter of the invention. Any and all objects are derived from the preferred forms of the invention, not necessarily the invention in general.
SUMMARY OF THE INVENTION
The present invention is directed to wordline row redundancy scheme circuitry including a row shift circuit and a row decoder circuit electrically coupled to the row shift circuit by a row shift control line. If row shift redundancy is not desired for a particular wordline, the row shift circuit applies a first row shift control signal to the row shift control line. If row shift redundancy is desired for that wordline, the row shift circuit applies a second row shift control signal to the row shift control line. The first and second row shift control signals have distinguishing characteristics. The signal applied to the row shift control line selectively actuates one of first and second electronic switches. At least one electronic switch is coupled in series to the first and second electronic switches. The first electronic switch is also electrically coupled in series to a first wordline select line. The second electronic switch is also electrically coupled in series to a second wordline select line corresponding to a wordline adjacent to the wordline corresponding with the first wordline select line. A row address line is electrically coupled to the at least one electronic switch to carry a row address selection control signal that selectively actuates the at least one electronic switch. A wordline driver line is also electrically coupled to the at least one electronic switch to carry a wordline select signal that passes through the at least one ele

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