Shift matrix preselector control circuit

Details Shift matrix preselector control circuit Shift matrix preselector control circuit

1983-06-28

1984-11-20

Thomas, James D.

Boots, shoes, and leggings

G06F 924, G06F 926, G06F 900

Patent

active

044842767

ABSTRACT:
A computer digital logic circuit utilizing an encoded Read Only Memory (ROM) and multiplexor elements is used to translate top-level shift control signals, such as arise from instruction translation, into the low-level control of selecting data input to, and controlling the shift count in, a shif matrix during a generalized computer shift operation. ROM size is held to only 64 addresses.times.16 bits per addressed cell in controlling selectable circular, selectable sign fill, single precision or double precision (dual pass) shifting in a sixteen bit shift matrix because the ROM is addressed with only part of the top-level shift control signals. Remaining top-level signals select among encoded outputs of the ROM in four multiplexor circuit elements to produce low-level gating control signals, called preselector control, which ultimately enable selection among two registers' data and sign fill data inputs to the shift matrix. The ROM directly produces the shift count control of the shift matrix. The combination of selection control and shift count control produced enables management of a shift matrix during general versatile shift operations, including double precision shifting.

REFERENCES:
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patent: 4195200 (1980-03-01), Feistel
patent: 4338675 (1982-07-01), Palmer et al.

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