Shift-correction code rate-enhancing parity encoding/decoding

Details Shift-correction code rate-enhancing parity encoding/decoding Shift-correction code rate-enhancing parity encoding/decoding

1990-12-26

1993-10-26

Baker, Stephen M.

Excavating

341 59, H03M 1300, H03M 746

Patent

active

052572706

ABSTRACT:
A method for coding/decoding ternary symbols to d,k-constrained binary runs in a way that (i) associates (codes) a number of ternary symbols with a lesser number of d,k-constrained binary runs and (ii) provides that an individual single-shift error in any of the received binary runs that constitute a binary data codeword will cause at most one ternary symbol to be in error in the associated (decoded) ternary symbol codeword. This method allows shift-correction codeword parity checks to be transmitted (i.e., transformed to a d,k-constrained channel data sequence) with increased efficiency, so that the required number of channel bits needed to represent the parity checks is decreased.

REFERENCES:
Bliss, W., "Circuitry for Performing Error Correction Calculations or Baseband Encoded Data to Eliminate Error Propagation", IBM Tech. Discl. Bull., vol. 23, No. 10, Mar. 1981, pp. 4633-4634.
Schneider, H., "Disk System ICs Combat Data Errors", Computer Design, Mar. 1985, pp. 147-152.

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