Shift-correcting code system with efficient symbol-to-channel bi

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341 59, 341 9A, 371 42, H03M 746, H03M 1300, G11B 2018

Patent

active

052710165

ABSTRACT:
In a shift-correcting code which represents (d,k)-constrained run-length-limited (RLL) channel data as symbols drawn from GF(p.sup.m), the encoding process produces a set of redundant parity ternary GF(p.sup.m) symbols representing three shift error conditions: forward shift, backward shift and no shift, for p=3 and m=1 for example. The encoder of the invention transforms the parity symbols into (d,k)-constrained RLL channel bits to produce a binary data sequence that can be inserted in the RLL channel data stream without a large number of linking bits to maintain compliance with the (d,k) RLL constraints. A shift error in the RLL channel data representing parity symbols affects no more than one decoded parity symbol. The encoder of the invention efficiently transforms ternary symbols into (d,k)-constrained binary data by coding successive ternary symbols into one of six binary channel words in accordance with (a) the contents of the input ternary symbol and (b) the current state of the encoder, and sets its state to one of two states in preparation for encoding the next ternary symbol. In the first state, the encoder generates one of three channel words each comprising two bits preceded by b zeroes and in the second state generates one of three channel words each comprising two bits preceded by a one and b-1 zeroes, where b is related to d and k so as to maintain the (d,k)-constraints of a number of practically useful RLL codes.

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