Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation
Reexamination Certificate
2000-08-04
2004-02-10
Wille, Douglas (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Electromagnetic or particle radiation
C257S459000
Reexamination Certificate
active
06690078
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed toward an improved photodiode structure.
2. Description of the Related Art
Photodiodes are diodes in which charge carriers are generated responsive to light incident upon the photodiode. Any PN junction diode which admits light can function as a photodiode. A photodiode outputs voltage or current when absorbing light. In a photodiode which is intended for high speed communication systems, it is important to optimize the performance for light conversion efficiency, speed (minimal transit time delay), minimum RC time constant, ability to operate at low reverse bias voltage, and cost in the application in which the photodiode will be employed.
FIG. 1
illustrates the structure of a conventional PIN photodiode
10
. A wafer
12
is lightly doped with N dopant in order to produce an intrinsic region
16
. A P+ region
14
is formed on one surface of the wafer and an N+ region
18
is formed on the opposing surface of wafer
12
with intrinsic region
16
interposed P+ region
14
and N+ region
18
. A reflective layer
20
is disposed on the surface containing N+ region
18
with reflective layer
20
also acting as the electrical contact to N+ region
18
. A metal contact ring
22
is disposed on the surface containing P+ region
14
to provide the electrical connection to the P+ region.
Typically, one power supply potential is applied to the reflective layer and another power supply voltage is applied to contact
22
to reverse bias the PN junction formed by P+ region
14
and N+ region
18
. This forms a depletion region
17
within the intrinsic region
16
wherein electron and hole charge carrier pairs generated by light photons incident upon the intrinsic region
16
are rapidly accelerated toward the P+ and N+ regions respectively by the electric field of the reverse bias voltage. Charge carrier pairs are also typically generated outside the depletion region
17
in non-depletion regions
24
A and
24
B of intrinsic region
16
and diffuse, due to random thermal motion of the carriers, at a much slower velocity until they reach either depletion region
17
or the junction formed by P+ region
14
and intrinsic region
16
of photodiode
10
.
A conventional photodiode that is designed for high quantum, i.e. light conversion, efficiency requires that the light path within the photo current collection zone, the non-depletion
24
and depletion
17
regions, be sufficient in length so that most of the light photons of the incident light signal are absorbed and converted into electron-hole pairs that are collectable at the P
+
and N
+
regions. Usually, this requires that the width W
2
of the intrinsic region
16
, which is the primary collection region between the P
+
14
and N
+
18
regions, be several times the length required for light absorption. If diode
10
has an efficient back-side reflector, such as reflective layer
20
, which effectively doubles the light path within diode
10
, then the intrinsic region
16
of the photodiode can be made narrower. For a typical near infrared silicon photodiode, the nominal absorption path length is about 15-25 microns. The path length should be at least two to three times the nominal absorption path length to obtain good light conversion efficiency.
On the other hand, a photodiode designed for high frequency response requires that the photo current pairs generated by the light signal be collected rapidly and that the diode RC time constant is fast. Rapid photo current pair collection usually requires that most of the photo current pairs generated by the light signal be generated within the depletion region
17
which has a high drift velocity when reversed biased. Otherwise, the photo generated charge carrier pairs produced in the non-depletion regions
24
A and
24
B outside the depletion region
17
, but within the diffusion distance of the collection electrodes
14
and
18
, will have a diffusion velocity which is several hundred times slower than the velocity of the pairs generated within the depletion region
17
. The photo generated charge carrier pairs in non-depletion regions
24
A and
24
B will slowly migrate for collection at P+ region
14
and N+ region
18
resulting in a tail on the trailing edge of the electrical signal corresponding to the light signal. The diffusion distance of the charge carriers is determined by the carrier mean free path before re-combination and may exceed 150 microns.
A fast RC time constant for photodiode
10
requires minimal capacitance and low series resistance between the electrical contacts
20
and
22
and the photo current pair collection sites at the margin between the depletion region
17
and P+ region
14
and the margin between depletion region
17
and N+ region
18
. The greater the width W
2
of the depletion layer
16
, then the lower will be the capacitance per unit area of photodiode
10
. Since the depletion width of the depletion region formed between P+ region
14
and N+ region
18
increases with the level of the reverse bias voltage, it is typical for high speed photodiodes to have a relatively high reverse voltage applied to them.
The inclusion of the separate lightly doped intrinsic region
16
between the P
+
and N
+
regions
14
and
18
results in a PIN diode with a wider depletion region
17
, depending on reverse bias voltage, which improves the light collection efficiency, speed, and reduces capacitance over that of a simple PN photodiode structure. Tailoring the width of the intrinsic region
16
allows for enhanced performance and tradeoffs for photodiode light conversion efficiency, response speed, and capacitance.
For example, a near infrared photodiode intended for use in a high speed, low cost IrDA data receiver operating from a 2.7V-5V power supply should ideally have an intrinsic layer width W
2
of about 20-40 microns wide to allow for good light absorption efficiency and to allow for full depletion of the intrinsic region
16
with a low 1-3V reverse bias, since typically not all of the power supply voltage is available for reverse bias. Such a diode will achieve minimal transit delay, less than 1 nanoseconds (ns), a minimal RC time constant, and optimal high current frequency response with low resistance in the intrinsic region
16
.
Although a PIN photodiode outperforms a standard PN diode, it cannot be easily manufactured by standard semiconductor processes wherein fabrication is typically performed on only one side of the semiconductor wafer
12
.
A PIN photodiode is typically produced by diffusing the N
+
diffusion region
18
on the back side of the lightly doped (N) wafer
12
, diffusing the P
+
diffusion region
14
on the topside of wafer
12
, and then adding metal contacts to each side of the wafer. Typically, the backside contact area connected to N+ region
18
is reflective layer
20
and is made of gold. The topside contact area
22
is an aluminum collector ring that is connected to P+ diffusion region
14
. The intrinsic or depletion layer depth W
2
is determined by the wafer starting thickness W
1
less the thickness of the N
+
18
and P
+
14
diffusion regions. Since standard silicon wafers are 350-500 microns in thickness and N+ and P+ diffusions are only a few microns thick, this typically results in an intrinsic layer width W
2
of 345-495 microns.
An improvement to the PIN manufacturing process described above is to lap the width W
1
of the starting wafer
12
to as thin as 100 microns, which will reduce the intrinsic layer width W
2
to about 95 microns. However, it is generally not practical to thin wafers beyond this limit without an excessive level of wafer breakage along with severe wafer handling and processing problems.
A PIN diode with an intrinsic region width W
2
of 95 microns typically requires more than a 5V reverse bias to be applied to the P+ and N&pl
Colaco Stephen F.
Holcombe Wayne T.
Irissou Pierre R.
North Brian B.
Francissen Vernon W.
Gardner & Carton & Douglas LLP
Integration Associates Inc.
Wille Douglas
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