Shielded delay line and method of manufacture

Details Shielded delay line and method of manufacture Shielded delay line and method of manufacture

1996-07-29

1998-09-15

Kincaid, Kristine L.

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

333161, 361777, 29850, H05K 100

Patent

active

058082417

ABSTRACT:
A thin film transmission line, delay line constructed on a ceramic substrate. A serpentine, transmission line conductor and a surrounding, coplanar border ground are plated in registry onto the substrate. Discrete ground paths which project from the border are interspersed between the conductor windings to electrically shield adjacent windings. A hard coat epoxy resin covers the signal layer, which may support a sputtered ground plane that is connected to the border ground. An alternative delay line provides overlying ground fingers within the dielectric covering layer which are aligned to the channel spaces between the conductor windings. Both assemblies provide an increased number of conductor lines per chip. Edge coupled terminations are provided at the substrate to accommodate multi-layer assemblies of the delay line and/or circuit terminations.

REFERENCES:
patent: 2832935 (1958-04-01), Tank
patent: 3257629 (1966-06-01), Kornreich
patent: 4614922 (1986-09-01), Bauman et al.
patent: 4641113 (1987-02-01), Ozawa
patent: 4641114 (1987-02-01), Person
patent: 5030931 (1991-07-01), Brooks et al.
patent: 5146191 (1992-09-01), Mandai et al.
patent: 5164692 (1992-11-01), Gertel et al.
patent: 5365203 (1994-11-01), Nakamura et al.
patent: 5398046 (1995-03-01), Szegedi et al.
patent: 5499442 (1996-03-01), Nakamura et al.

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