Shielded bit line architecture for memory arrays

Details Shielded bit line architecture for memory arrays Shielded bit line architecture for memory arrays

2000-06-23

2001-10-16

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S206000

Reexamination Certificate

active

06304479

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to architectures of memory arrays and more particularly, to a shielded bit line architecture to reduce signal coupling to adjacent bitlines in a memory array.
2. Description of the Related Art
Semiconductor memories include bitlines, which are connected to memory cells to read and write data to the memory cell. The impetus for higher density devices has made the elimination of cross-talk or cross-coupling between bitlines an even more challenging task. Referring to
FIG. 1
, a layout of a conventional folded bitline architecture
10
is shown. Architecture
10
includes a plurality of sense amplifiers SA each for sensing two bitlines
12
. Memory cells
14
store data, and in this example, all memory cells
14
store a “1”, as indicated in the “Data” column of FIG.
1
. During a read, a cell signal on bitline
12
1
is attenuated by cross-coupling to both adjacent bit lines
12
2
and
12
3
. This reduces the differential signal of the sense amplifier
16
1
.
As indicated in
FIG. 1
, considering bitline
12
1
, cross-coupling influences, shown by arrows
18
, effect the data read from memory cell
14
1
on bitlines
12
1
and
12
2
. Surrounding components such as adjacent bitlines
12
3
and
12
2
as well as sense amplifiers
16
2
,
16
3
and
16
4
, all effect the signal on bitline
12
1
. Bitlines
12
3
and
12
2
experience inter bitline cross-coupling, while sense amplifiers
16
2
,
16
3
and
16
4
affect the signal on bitline
12
1
due to sensing mismatches (also capacitive coupling) caused by attempting to read “1”s from nearby memory cells. Sense amplifier
16
3
influences are negligible.
Referring to
FIG. 2
, an illustrative diagram is shown for quantifying the effects of surrounding components on a signal on bitline
12
1
. Each line labeled in
FIG. 2
represents the effect on voltage that each corresponding component of
FIG. 1
has on the signal on bitline
12
1
. Taken from the perspective of bitline
12
1
, surrounding components influence a signal to be sensed by sense amplifier
16
1
on bitline
12
1
. Sense amplifier
16
1
sees effects due to bitlines
12
3
,
12
4
, and
12
2
(
FIG. 2
shows two influences on bitline
12
1
, one from inactive bitline
12
2
and one due to the influences of active bitline
12
4
through bitline
12
2
). Sense amplifier
16
1
therefore sees a relative loss of −5.5 as indicated in box
15
. This relative term is a multiplier, which represents a multiple of a coupling percent. A bar
17
is indicated showing the relative differential measured by sense amplifier
16
1
due to the coupling effects an sensing mismatches. For example, if cross coupling loss is 5% for each component adjacent to bitline
12
1
, a signal loss of 27.% (−5.5 times 5%) is experienced. In architecture
10
, relatively high coupling losses are experienced.
Referring to
FIG. 3
, a twisted bitline architecture
20
is shown. Architecture
20
includes a plurality of sense amplifiers SA each for sensing two bitlines
22
. Memory cells
24
store data, and in this example, memory cells
24
1
and
24
2
store a “1”. Memory cell
24
3
stores a “0” and
24
4
can be a “1” or a “0”. During sensing if one bitline associated with a sense amplifier
26
goes up, and the other goes down the charge is equally distributed to the next line and there is no net effect to the next adjacent bitline. However, if only one line is pulled up and the other stays at the same level, some signal is coupled which disturbs the next adjacent cell. In
FIG. 3
, signal is coupled to adjacent bitlines
22
and sense amplifiers
26
from bitline
22
1
. During a read, a cell signal on bitline
22
1
is attenuated by cross-coupling to adjacent bit lines
22
2
,
22
3
22
4
and
22
5
and to sense amplifiers
26
2
and
26
3
.
As indicated in
FIG. 3
, considering bitline
22
1
, cross-coupling influences
28
affect the data read from memory cell
24
1
on bitlines
22
1
and
22
2
. Surrounding components such as adjacent bitlines
22
3
and
22
2
as well as sense amplifiers
26
2
,
26
3
and
26
4
, all effect the signal on bitline
22
1
. Bitlines
22
3
and
22
2
experience inter-bitline cross-coupling, while sense amplifiers
26
2
affects the signal on bitline
22
1
due to sensing mismatches (also capacitive coupling). Sense amplifier
26
3
influences are negligible.
Referring to
FIG. 4
, an illustrative diagram is shown for quantifying the effects of surrounding components on a signal on bitline
22
1
. Each line labeled in
FIG. 4
represents the effect on voltage that each corresponding component of
FIG. 3
has on the signal on bitline
22
1
. Sense amplifier
26
1
therefore sees a relative loss of −4.5, as indicated in box
25
. This relative term is a multiplier, which represents a multiple of a coupling percent. A bar
27
is indicated showing the relative differential measured by sense amplifier
26
1
due to the coupling effects an sensing mismatches. For example, if cross coupling loss is 5% for each component adjacent to bitline
22
1
, a signal loss of 17.% (−4.5 times 5%) is experienced. In architecture
20
, high coupling losses are experienced however coupling is less than the folded bitline architecture.
Referring to
FIG. 5
, another example of the twisted bitline architecture
20
includes memory cells
24
which all store “1”s, which are to be read simultaneously. Influences
28
are less since adjacent bitlines are affected by one half of the twisted bitlines and a more symmetric activation of pairs of bitlines provides local cancellations of capacitive coupling. During sensing in this arrangement, one bitline associated with a sense amplifier
26
goes up, and the other goes down, and charge is equally distributed to the next line and there is no net effect to the next adjacent bitline.
As indicated in
FIG. 5
, considering bitline
22
3
, cross-coupling influences
28
affect the data read from memory cell
24
3
on bitline
22
3
. Surrounding components such as adjacent bitlines
22
1
and
22
6
as well as sense amplifier
26
3
, affect the signal on bitline
22
3
. Note that sense amplifier
26
3
affects the signal on bitline
22
3
due to sensing mismatches.
Referring to
FIG. 6
, an illustrative diagram is shown for quantifying the effects of surrounding components on a signal on bitline
22
3
. Each line labeled in
FIG. 6
represents the effect on voltage that each corresponding component of
FIG. 5
has on the signal on bitline
22
3
. Sense amplifier
26
2
therefore sees a relative loss of −3.5 as indicated in box
25
. This relative term is a multiplier, which represents a multiple of a coupling percent. A bar
27
′ is indicated showing the relative differential measured by sense amplifier
26
1
due to the coupling effects and sensing mismatches. For example, if cross coupling loss is 5% for each component adjacent to bitline
22
1
, a signal loss of 17.5% (−3.5 times 5%) is experienced. Coupling is less for the loading shown in FIG.
5
.
Referring to
FIG. 7
, a double twisted bitline architecture
30
is shown. Architecture
30
includes twisted bitline pairs, which preferably have different twist pitches in alternating pair positions, as shown. A signal on bitline
32
1
is coupled to the second bitline
32
2
, which is connected to a sense amplifier
36
1
. The differential signal is reduced by a small amount only and due to the double twisting only a few influences
38
of cross-coupling are experienced, namely influences by bitlines
32
2
and
32
3
. Sense amplifier
36
2
influences are negligible.
Referring to
FIG. 8
, an illustrative diagram is shown for quantifying the effects of surrounding components on a signal on bitline
32
1
. Each line labeled in
FIG. 8
represents the effect on voltage that each corresponding component of
FIG. 7
has on the signal on bitline
32
1
. Sense amplifier
36
1
therefore sees a relative loss of only −3.0, as indicated in box
35
. This relative term is a multiplier, which repre

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