Sharing physical memory locations in memory devices

Details Sharing physical memory locations in memory devices Sharing physical memory locations in memory devices

2011-01-04

2011-01-04

Patel, Hetul (Department: 2186)

Static information storage and retrieval

Floating gate

Particular connection

C365S096000, C365S225700, C711S104000, C711S105000

Reexamination Certificate

active

07864577

ABSTRACT:
A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.

REFERENCES:
patent: 5999463 (1999-12-01), Park et al.
patent: 6480429 (2002-11-01), Jones et al.
patent: 7046560 (2006-05-01), Ayyapureddi et al.

Affiliated with

Also associated with

Rating

Sharing physical memory locations in memory devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sharing physical memory locations in memory devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sharing physical memory locations in memory devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2708493