Sharing of bus access among multiple state machines with minimal

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395725, 36424291, 36424292, 364DIG1, 36493701, 364DIG2, G06F 1314

Patent

active

052652122

ABSTRACT:
Conflicting users of a shared resource are controlled by respective state machines having cross-coupled busy signals permitting each user to proceed with exclusive use of the shared resource when the other users are finished using the resource. Priority logic responsive to service requests issues grant signals to the state machines so that the state machines do not permit their respective users to begin simultaneously exclusive use of the resource. Preferably, each state machine also receives the requests for service of its respective user. Each state machine, for example, has an idle state, a first state reached from the idle state in response to a service request; a second state reached from the first state in response to a grant signal; and a third state reached from the second state, unless the busy signal of another state machine is asserted. Preferably, each state machine is responsive to a request having different preassigned priorities. The priority logic arbitrates among requests for services of different users, and each state machine arbitrates among the requests of different priorities for the service of its respective user. In a specific example, the users are DRAM memory banks that share a common data bus. The requests include read requests, write requests, and refresh requests. Read requests are given priority over write requests.

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