Shared synchronous memory multiprocessing arrangement

Details Shared synchronous memory multiprocessing arrangement Shared synchronous memory multiprocessing arrangement

1978-06-16

1980-06-24

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1300, G06F 1516

Patent

active

042098394

ABSTRACT:
A multiprocessor system is described which allows for the sharing of memories between the individual processors having synchronous memory interfaces. Three processing units are shown by way of example, each processor having its own local, associated memory. Two of the processing units can each access its own memory but not any other memory. The third processing unit can access its own memory as well as the memories associated with the other two processing units. An engine interface adapter interconnects the I/O busses of the processing units. The functions performed by the engine interface adapter can be divided into two principal groups. The first group of functions permits communication between the processors via their I/O busses. The second group of functions permits the aforedescribed sharing of the memory units between the processing units.

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Anacker et al., "Data Distribution Channel for Multiprocessor Systems," IBM TDB vol. 9, No. 9, Feb. 1967, pp. 1145-1147.

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