Shared row decoder

Details Shared row decoder Shared row decoder

1998-02-02

2000-09-12

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, G11C 800

Patent

active

061187267

ABSTRACT:
A shared row decoder and shared row decoding method are disclosed herein which provides separate timed selection signals to each of a first memory unit and a second memory unit. The shared row decoder includes an address input circuit responsive to the states of a plurality of address signals and which provides an enabling or disabling input. In addition, first and second selection circuits are provided which are responsive to enabled conditions of first and second block selection inputs, first and second timing signals, respectively and enabling input of the address input circuit to provide separate timed selection signals to the first and second memory units, respectively.

REFERENCES:
patent: 4384347 (1983-05-01), Nakano
patent: 4393472 (1983-07-01), Shimada et al.
patent: 4758993 (1988-07-01), Takemae
patent: 5091851 (1992-02-01), Shelton et al.
patent: 5267215 (1993-11-01), Tsujimoto
patent: 5289417 (1994-02-01), Ooishi et al.
patent: 5315548 (1994-05-01), Ooishi et al.
patent: 5327389 (1994-07-01), Seok et al.
patent: 5386385 (1995-01-01), Stephens, Jr.
patent: 5446700 (1995-08-01), Iwase
patent: 5502675 (1996-03-01), Kohno et al.
patent: 5519650 (1996-05-01), Ichimura et al.
patent: 5610871 (1997-03-01), Hidaka
Y. Kodama et al., "A 150-MHz 4-Bank 64M-bit SDRAM with Address Incrementing Pipeline Scheme", 1994 IEEE, Symposium on VLSI Circuits Digest of Technical Papers, pp. 81-82.
G. Bronner et al. "A Fully Planarized 0.25um CMOS Technology for 256Mbit DRAM and Beyond", 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 15-16.
T. Saeki et al. "A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay", 1996 IEEE International Solid-State Circuits Conference.
T. Kirihata et al., "Fault-Tolerant Designs for 256 Mb DRAM", IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Apr. 1996, pp. 558-566.
Y. Watanabe et al., "A 286 mm2 256 Mb DRAM with x 32 Both-Ends DQ", IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Apr. 1996, pp. 567-574.
J. Yoo et al., "A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 GByte/s Bandwidth", IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1635-1644.

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