Shared rounding hardware for multiplier and divider/square root

Details Shared rounding hardware for multiplier and divider/square root Shared rounding hardware for multiplier and divider/square root

1995-07-05

1997-09-23

Malzahn, David H.

Boots, shoes, and leggings

G06F 752, G06F 7552

Patent

active

056711719

ABSTRACT:
A floating point mantissa final addition and rounding unit uses a conditional sum adder to reduce a redundant carry-save format 106-bit mantissa to a non-redundant properly rounded 53-bit double-precision mantissa. The conditional sum adder simultaneously speculatively computes both the sum and the incremented sum of the upper 52 bits of the carry-save portions. A rounding unit speculatively computes the lower one bit and two bits of the mantissa for the cases of mantissa overflow or non-overflow, respectively. The rounding unit produces an overflow carry signal and a non-overflow carry signal. A multiplexor selects the proper 53 mantissa output bits from among the two conditional sum adder outputs and the rounding unit mantissa outputs depending upon the most significant bits of the two conditional sum adder outputs and the overflow and non-overflow carry signals. The floating point mantissa final addition and rounding unit is used to perform the final addition and rounding for a multiplier that produces a 106-bit carry-save result and for a division/square root unit that produces a 56-bit non-redundant result. A multiplexor selects the input from among the multiplier carry-save result and the division/square root unit non-redundant result. When the division/square root result is selected, the carry portion and the less significant 50 bits of the sum portion are set equal to zero. When a non-redundant result is input into the final addition and rounding unit, the conditional sum adder acts merely as an incrementer.

REFERENCES:
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patent: 5511016 (1996-04-01), Bechade
Claude P. Lerouge, Pierre Girard, Joel S. Colardelle, "A Fast 16 Bit NMOS Parallel Multiplier", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 3, Jun. 1984.
Ramautar Sharma, Alexander D. Lopez, John A. Michejda, Steven J. Hillenius, John M. Andrews, Arnold J. Studwell, "A 6.75-ns 16.times.16-bit Multiplier in Single-Level-Metal CMOS Technology", IEEE Journal of Solid-State Circuits, vol. 24, No. 4, Aug. 1989.
W.K. Luk, J.E. Vuillemin, "Recursive Implementation of Optimal Time VLSI Integer Multipliers", 1983.

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