Shared redundancy programming of memory with plural access ports

Details Shared redundancy programming of memory with plural access ports Shared redundancy programming of memory with plural access ports

1995-06-13

1998-07-28

Robertson, David L.

Excavating

G11C 700

Patent

active

057870918

ABSTRACT:
The circuit of this invention includes a programmable circuit (PC) for storing an internal address and for producing logic levels (LL1, etc.) determined by that internal address and includes a first comparison circuit (CC1) and a second comparison circuit (CC2). The first comparison circuit (CC1) responds to the logic levels (LL1, etc.) representative of that internal address and to a first address signal (CA0, etc.) to generate a first match signal (CRFSN) determined by matching of the internal address and the first address signal (CA0, etc.). The second comparison circuit (CC2) responds to the logic levels (LL1) and to a second address signal (SF0, etc.) to generate a second match signal (SRSJN) determined by the matching of the internal address and the second address signal (SF0, etc.).

REFERENCES:
patent: 5258953 (1993-11-01), Tsujimoto
patent: 5278793 (1994-01-01), Yeh
patent: 5347489 (1994-09-01), Kwong et al.
patent: 5379259 (1995-01-01), Fujita
patent: 5469601 (1995-11-01), Gillingham
patent: 5528539 (1996-06-01), Ong et al.

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