Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1993-03-01
2000-08-29
Ellis, Richard L.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
G06F 15173
Patent
active
061122874
ABSTRACT:
A multiprocessor system comprising a core memory (RAM), processing units (CPU.sub.1 -CPU.sub.j), each being provided with a cache memory (MCj), a directory (RG.sub.j) and a management processor (PG.sub.j); the core memory (RAM) is connected to an assembly of shift registers (RDM.sub.1 -RDM.sub.j) in such a way as to permit, in one cycle of the memory, a parallel transfer by reading or writing of data blocks; each cache memory (MC.sub.j) is connected to a shift register (RDP.sub.j)in such a way as to permit a parallel transfer by reading or writing of data blocks. An assembly of series connections, (LS.sub.1 -LS.sub.n) is provided between the assembly of memory shift registers and the assembly of processor shift registers to permit the transfer of data blocks between each pair of associated registers (RDM.sub.j -RDP.sub.j); the addresses of the data blocks can be transmitted between processor (CPU.sub.j) and the core memory (RAM) either by the series connections or by a common address bus (BUS A). The architecture according to the invention makes it possible to provide a large number of processing units while obtaining a high output from each processor.
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Elkhlifi Fatima-Zahra
Lalam Mustapha
Litaize Daniel
Mzoughi Abdelaziz
Sainrat Pascal
Busless Computers Sarl
Dutton, Jr. Harold H.
Ellis Richard L.
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