Electrical computers and digital processing systems: multicomput – Computer-to-computer direct memory accessing
Reexamination Certificate
2007-04-17
2007-04-17
Winder, Patrice (Department: 2145)
Electrical computers and digital processing systems: multicomput
Computer-to-computer direct memory accessing
C709S215000, C709S223000
Reexamination Certificate
active
10632856
ABSTRACT:
Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.
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“The Stanford FLASH Multiprocessor”, the 21stAnnual I.S.C.A proceedings, by Jeffrey Kuskin, et al., pp. 302-313.
Akashi Hideya
Hamanaka Naoki
Irie Naohiko
Okochi Toshio
Shonai Toru
Hitachi , Ltd.
Mattingly ,Stanger ,Malur & Brundidge, P.C.
Mirza Adnan M.
Winder Patrice
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