Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
2000-02-04
2001-11-13
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S541000, C345S503000, C345S545000
Reexamination Certificate
active
06317135
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the visual display of a computer graphics image and, in particular, to a graphics display system that integrates both a graphics accelerator engine and a portion of the graphics frame buffer memory on the same monolithic chip.
2. Discussion of the Prior Art
A video graphics system typically used either VRAM or DRAM frame buffers to store the pixel display data utilized in displaying a graphics or video image on a display element such as a CRT.
A VRAM frame buffer includes two ports that are available for the pixel data to flow from the memory to the display. One port is known as the serial port and is totally dedicated to refreshing the display screen image. The other port is a random access port that is used for receiving pixel updates generated by a CPU or a graphics accelerator engine. A typical VRAM arrangement allocates 99% of the available bandwidth to the random port thereby allowing the system to display fast moving objects and to support large display CRTs.
However, in a DRAM-based video system, the pixel data updates and the screen refresh data contend for a single frame buffer memory port. This connection reduces the amount of bandwidth available for pixel data updates by the CPU and the graphics engine, resulting in a lower performance graphics display system.
However, in most applications the DRAM solution is preferable to the VRAM solution at the expense of lower performance, because DRAMs are cheaper than VRAMs.
FIG. 1
shows a conventional graphics display system
10
wherein a CPU
12
writes pixel display data on data bus
11
to be displayed on the CRT screen
14
through a graphics accelerator (GXX)
16
onto a DRAM frame buffer
18
via data bus
19
. The CPU
12
also provides certain higher level graphics command signals
20
to the graphics accelerator
16
to manipulate the display data stored in the DRAM frame buffer
18
.
The graphics accelerator
16
retrieves display data from the frame buffer
18
via data bus
19
utilizing reference address bus
21
, processes the retrieved display data based on the CPU command signals
20
and writes the new pixel data back to the frame buffer
18
.
The pixel data is displayed on the CRT
14
through a random access memory digital-to-analog converter (RAMDAC)
22
that receives the data via a data display bus
24
.
The graphics accelerator
16
also constantly reads display data from the frame buffer
18
via data bus
19
and sends it to the RAMDAC
22
via the data display bus
24
to meet the refresh requirements of the CRT display
14
.
Thus, as illustrated in
FIG. 1
, the bandwidth of the data bus
19
is shared by three functions: display refresh, CPU display data update, and graphics accelerator display manipulation. As the display size (i.e., the number of pixels to be displayed on the CRT screen
14
) increases, the display updates and display manipulation functions are reduced because of the bandwidth limitations of the data bus
19
caused by the fixed refresh requirements of the CRT
14
.
While these limitations can be addressed by increasing the data bus width or by increasing its speed, both of these solutions have either physical or practical limitations. Increasing the bus width increases the silicon area and the package pin count. Increasing the speed of the bus requires utilization of more complex silicon process technology.
SUMMARY OF THE INVENTION
The present invention provides a graphics display system that enhances performance by integrating a portion of the frame buffer storage space and the graphics accelerator engine on the same chip while at the same time maintaining the flexibility to expand the frame buffer size as needed.
Generally, the present invention provides a shared memory graphics accelerator system that provides display data to a display element. The shared memory graphics accelerator system includes a central processing unit that generates both display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator that receives display data and graphics commands from the central processing unit and an on-chip frame buffer memory element that is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes the display data to the on-chip memory element and to the off-chip memory element based on predefined display data distribution criteria.
The above-described integrated solution increases the performance of the graphics display system because display data retrieval from the on-chip frame buffer is much faster than from an external frame buffer and the DRAM timing constraints are reduced, thus achieving improved system performance. This integrated solution also allows the display memory size to be expanded by adding external memory so that large displays can be accommodated on an as-needed basis. Also, the frame buffer space can be distributed among several integrated solutions, thereby increasing both the display bandwidth and the parallel processing capability between the CRT display and the CPU.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized.
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Alliance Semiconductor Corporation
Finnegan Henderson Farabow Garrett & Dunner LLP
Tung Kee M.
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