Shared memory device with arbitration to allow uninterrupted acc

Details Shared memory device with arbitration to allow uninterrupted acc Shared memory device with arbitration to allow uninterrupted acc

1997-03-07

1998-06-09

Swann, Tod R.

Boots, shoes, and leggings

364DIG1, 3642461, 395478, 395481, 395485, G06F 1200, G06F 1300

Patent

active

057650365

ABSTRACT:
A shared memory system (10) is provided which interfaces with a shared memory bus (14). The shared memory bus (14) interfaces with a plurality of peripherals (12) through memory interfaces (16). Each of the memory interfaces (16) is operable to receive addresses from the associated one of the peripheral units (12) and communicate with the shared memory system (10) to process the addresses and subsequent data transfers in an ordered manner. The shared memory system (10) has associated therewith an arbitration logic circuit (78) that is operable to service bus requests from each of the memory interfaces (16). When a bus request is received, the requesting one of the memory interfaces (16) is allowed to access a single byte of data, after which it relinquishes the bus to another one of the memory interfaces (16). The previous requesting one of the buses that performed the one byte data transfer operation is then lowered in its priority such that all the requesting ones of the memory interfaces (16) are allowed to transfer at least one byte of data. This results in a byte-by-byte transfer of data without allowing any one of the memory interfaces (16) to seize and hold the bus for multiple data transfers in a sequential manner. In another mode, each of the memory interfaces (16) is allowed to seize the bus to continuously transfer data with a priority system implemented to allow a higher priority one to seize the bus away from the lower priority one.

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