Shared memory based network switch and the network...

Details Shared memory based network switch and the network... Shared memory based network switch and the network...

1999-07-09

2003-03-18

Olms, Douglas (Department: 2732)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S412000

Reexamination Certificate

active

06535516

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a network switch and a network adapted for use with the network switch. In particular, the invention relates to a shared memory based network switch and a network constructed with the same, in which each network switch has a stack, several queues corresponding to output ports and a shared control port, so that the shared memory can be used more efficiently.
2. Description of the Related Art
Ethernet switch ICs are usually divided into three categories: shared bus based architecture, cross bar based architecture and shared memory base architecture.
FIG. 1
(Prior Art) is a diagram showing a conventional shared bus based architecture. As shown in
FIG. 1
, Ethernet switch ICs ESW
1
~ESW
4
are respectively provided with a local packet memory PM
1
~PM
4
. When one of the Ethernet switch ICs receives an incoming packet, that Ethernet switch IC will make a local routing decision and write the packet to a free buffer of its local packet memory. If the packet is to be outputted to a destination port within the range of the original Ethernet switch IC, the packet is passed directly to the destination port. If the packet is to be outputted to a destination port outside the range of the original Ethernet switch IC, then the Ethernet switch IC will send a command through the shared bus and command the destined Ethernet switch IC to prepare a free buffer. The original Ethernet switch then sends the packet through the shared bus to the destined Ethernet switch and releases the storage space. Thereafter, the destined Ethernet switch IC stores the packet and outputs the packet to the destination port.
FIG. 2
(Prior Art) is a diagram showing a conventional cross bar based architecture. As shown in
FIG. 2
, Ethernet switch ICs ESW
5
~ESW
8
are connected to an arbitrator AR
1
and are respectively provided with a packet memory PM
5
~PM
8
. When one of the Ethernet switch ICs transfers an outgoing packet, this Ethernet switch IC will send a command to instruct the arbitrator AR
1
to establish a point-to-point interconnection, so that the packet can be sent from the transferring Ethernet switch IC to the destined Ethernet switch IC.
FIG. 3
(Prior Art) is a diagram showing a conventional point-to-point shared memory based architecture. As shown in
FIG. 3
, Ethernet switch ICs ESW
9
~ESW
12
are connected to a shared memory M
1
. A central queue manager COM
1
is used to control the shared memory M
1
, for example, by allocation or release of a free buffer (not shown) in the shared memory M
1
.
FIG. 4
(Prior Art) is a diagram showing a conventional meshed shared memory based architecture. As shown in
FIG. 4
, four Ethernet switch ICs ESW
13
~ESW
16
are interconnected to each other as a mesh (that is, each of the four Ethernet switch ICs is connected to the other three), and all packets are parallelly stored in four packet memories PM
13
~PM
16
which are dedicated to a respective one of the four Ethernet switch ICs ESW
13
~ESW
16
.
However, each of the mentioned architectures has its drawbacks.
In the shared bus based architecture of
FIG. 1
, when one of the Ethernet switch ICs receives an incoming packet, this Ethernet switch IC will store the packet in its local packet memory, then directly output the packet to a destination port (if the destination port is within the range of the original Ethernet switch IC) or indirectly output this packet through another destined Ethernet switch IC (if the destination port is outside the range of the original Ethernet switch IC). Using this architecture, it is possible for a packet to be moved and copied two or more times, which reduces the efficiency of the shared memory. Although this architecture can provide multicast services, its quality of services (QOS) is fair.
In the cross bar based architecture of
FIG. 2
, the arbitrator AR
1
is used to establish a point-to-point interconnection so that the packet can be transferred to the destined Ethernet switch IC. However, with this architecture, it takes a two-cycle await time to transfer a packet. Also, this cross bar based architecture cannot support multicast services or good quality of services. Head-of-line blocking is also possible.
In the point-to-point shared memory based architecture of
FIG. 3
, Ethernet switch ICs are connected to a shared memory. Therefore, it only takes a one-cycle await time to transfer a packet, and multicast services and good quality of services can be supported. However, an extra central queue manager is required, making single chip solutions impossible.
The meshed shared memory based architecture of
FIG. 4
also only requires a one-cycle await time to send a packet; multicast services and good quality of services can be supported; and single chip solutions can be supported. However, a meshed shared memory based architecture is complicated and does not allow for easy expansion.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a shared memory based network switch and a network including the same, the shared memory based network switch requiring only a one-cycle await time to transfer a packet.
It is another object of the present invention to provide a shared memory based network switch and a network including the same, which can support multicast services and good quality of services.
It is another object of the present invention to provide a shared memory base network switch and a network including the same, which can support single chip solutions and can be expanded easily because of its simple structure.
To realize the above and other objects, the present invention provides a shared memory based network including a transferring network switch and a receiving network switch. Each network switch includes a stack, several queues of corresponding output ports and a shared control port. The stack stores available buffer addresses of the shared memory. Each of the queues stores to-be-accessed buffer addresses of the corresponding output port. The shared control port is driven to indicate various states of the network, so that the stack of the transferring network switch is identical with the stacks of the receiving network switches at all times, and the shared memory is read by all the output ports of both the transferring network switch and the receiving network switch according to the corresponding queues.
The present invention also provides a shared memory based network switch which is connected to a shared memory through a shared bus. The shared memory includes several buffers. The network switch includes a stack, several queues corresponding to output ports and a shared control port. The stack stores available buffer addresses of the shared memory. Each of the queues stores to-be-accessed buffer addresses of the corresponding output port. The shared control port is driven to various states so that the stack can pop out or push in a top buffer address, and the shared memory can be read by all the output ports according to the corresponding queues.


REFERENCES:
patent: 5910928 (1999-06-01), Joffe
patent: 5920566 (1999-07-01), Hendel et al.

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