Shared memory architecture in GPS signal processing

Details Shared memory architecture in GPS signal processing Shared memory architecture in GPS signal processing

2005-08-16

2005-08-16

Sparks, Donald (Department: 2187)

Communications: directive radio wave systems and devices (e.g.,

Directive

Including a satellite

C342S357490, C342S357490, C375S134000, C375S137000, C375S142000, C375S150000, C375S343000, C700S002000, C700S004000, C700S005000, C701S213000, C701S214000, C701S215000, C711S129000, C711S130000, C711S147000, C711S148000, C711S153000, C711S170000, C711S173000

Reexamination Certificate

active

06930634

ABSTRACT:
A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

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