Shared memory architecture in GPS signal processing

Details Shared memory architecture in GPS signal processing Shared memory architecture in GPS signal processing

1999-12-16

2003-02-25

Gordon, Paul P. (Department: 2121)

Data processing: generic control systems or specific application

Generic control system, apparatus or process

Plural processors

C701S213000, C711S148000

Reexamination Certificate

active

06526322

ABSTRACT:

FIELD OF INVENTION
This invention relates to the field of GPS receivers.
BACKGROUND OF INVENTION
FIG. 1
illustrates a typical GPS radio receiver
10
, while
FIG. 2
provides a general flow chart illustrating the general operations of GPS receiver
10
such as a satellite signal acquisition, tracking, or re-acquisition, and navigational processing. As illustrated in the simplified block diagram of a typical GPS receiver
10
shown in
FIG. 1
, a signal processing block
20
is provided to perform satellite signal acquisition and processing on a digitized IF signal
19
received via receiver antenna
12
. Signal processing block
20
typically performs a two-dimensional search for a satellite signal, in time (code phase) and frequency. To decrease the amount of time needed for GPS signal acquisition in time, and frequency domains, a massively parallel architecture is usually required for searching in parallel a large number of code positions and frequency uncertainties. In the code phase search, the required number of code positions is directly related to initial time uncertainty. A large number of corellators allows a quick, parallel search of many code positions. In the frequency search, a large number of frequency bins architecture speeds up searching multiple frequency uncertainties in parallel, thereby reducing the total time for search.
As illustrated in
FIG. 1
, signal processing
20
consists of three functional stages: a first stage consists of channel correlation signal processing
22
that compares (or correlates) digitized signal
19
with a locally generated code that attempts to replicate the P or C/A code generated by a satellite. The replica code searches a “space” that consists of the unique codes generated by the different satellites, the temporal position of the code being sent at any given time, and the Doppler frequency offset caused by the relative motion of the satellite and user. Generally, correlator signal processing unit
22
can perform parallel correlations with multiple code/position/doppler combinations simultaneously in a multiple channel fashion, usually up to 12. The next functional stage of signal processing
20
comprises tracking processing unit
24
, typically provided by a tracking processing CPU. The tracking processing CPU uses correlator information from correlator signal processing unit
22
to ascertain the probability of correctness of a code/position/doppler combination and to “follow”, or track, that signal once it is found. Tracking processing unit
24
includes having the tracking CPU program the correlator signal processing unit
22
where to search for a GPS satellite signal. Once a signal is found and locked onto, the tracking CPU also extracts the 50 Hz modulated data that contains navigation information transmitted by the GPS satellite. Finally, a navigation processing unit
26
, comprising a navigation processing CPU, uses data collected by the correlator signal processing unit
22
and tracking processing unit
24
to perform the calculations to determine the user's position, velocity, and time.
In the typical GPS signal processing
20
, an associated and dedicated memory unit is coupled to each functional unit stage. Thus, correlator signal processing unit
22
is typically coupled to an associated dedicated correlation processing memory unit
28
shown in FIG.
1
. Coherent and non-coherent I & Q samples are stored in correlation processing memory
28
received from correlator signal processing unit
22
. Tracking processing unit
24
is coupled to a tracking unit memory
30
to store the code, data, and parameters utilized by the tracking processor CPU for acquisition and tracking processing such as, for example, carrier loops, code loops, code lock detect, costas lock detect, bit synchronization, data demodulation. Navigation processing unit
26
is coupled to a navigation processing memory
32
for storing the code and data for the navigation processing CPU, such as calculation of position and time.
Thus, in operation, typical GPS receiver
10
requires significant hardware and memory to search, utilizing a large number of correlators and multiple frequency bins to implement. For example, an 8 frequency bin search should reduce the search time by a factor of 8 but it will require 4 times the memory to store the coherent integration samples and 8 times the memory to store the non-coherent integration samples. In order to achieve low cost, commercial GPS receiver architectures are deterred from using massively parallel architectures to avoid the cost of massively parallel implementation. There is therefore a need for a GPS signal processing architecture that minimizes the costly memory requirement and still achieves extremely fast signal acquisition.
SUMMARY OF INVENTION
A shared memory architecture for a GPS receiver is provided, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.


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