Shared memory access control system for a multiprocessor system

Details Shared memory access control system for a multiprocessor system Shared memory access control system for a multiprocessor system

1976-02-18

1978-12-05

Chapnick, Melvin B.

Boots, shoes, and leggings

G06F 920, G06F 1300

Patent

active

041288815

ABSTRACT:
In a multiprocessor system having a plurality of processors, each of identical construction, each processor is internally equipped with a fixed address supply source which generates a non-unique fixed address for accessing a common memory unit over commonly connected bus lines, and a sequential state indicate signal generator for generating a logic "1" or "0" synchronizing signal when a special condition (for example, interrupt) occurs with respect to the processor.
A shared memory access control system for a multiprocessor system, as above described, includes circuitry, external to and associated with at least each processor except for one processor, responsive to the synchronizing signal from its respective processor for modifying the non-unique fixed address from the respective processor so that, as a result, each processor is able to address the common memory over the commonly connected bus lines with a unique fixed address.

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patent: 3931505 (1976-01-01), Sevcik
patent: 3982231 (1976-09-01), Bernstein et al.

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