Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-05-08
2001-04-24
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06223196
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a shared MAC (Multiply Accumulate) system and a method therefor, and in particular to a method whereby a MAC unit of a sub-processor is employed in common by the sub-processor and a host processor.
2. Prior Art
For a low end application, an integrated dual processor module that provides a high performance at low cost has been proposed for which a host processor and a sub-processor are integrated in a single chip and are independently operated. A host processor can be, for example, a CISC microcontroller for controlling the entire apparatus, and a sub-processor can be, for example, a fuzzy processor for performing a DSP function.
FIG. 1
is a block diagram illustrating the arrangement of a conventional integrated dual processor module. A CISC host processor
1
and a sub-processor
2
are connected by a host bus interface
3
. In the sub-processor
2
are provided a memory
4
and a multiply accumulate (MAC) unit
5
, which performs the important function required of the sub-processor
2
. The MAC unit
5
of the sub-processor
2
normally performs a routine process, such as servo control for which repetitious MAC operations are required, while the microprocessor
1
is primarily responsible for overall system control. The exchange of data by means of interrupt signals transmitted via a memory or a register that is used in common has been proposed as a method by which the two processors can communicate.
In the conventional system, if a single MAC operation must be performed in a processing sequence handled by the host processor
1
, either a multiplication instruction and an addition instruction provided for the host processor
1
must be combined to perform the MAC operation, or interrupt processing must be performed to assign the execution of the MAC operation to the MAC unit
5
in the sub-processor
2
. In either case, however, a relatively long execution time is required for the processing. Particularly in the latter case, where the host processor
1
employs the interrupt process to assign the MAC operation to the sub-processor
2
, the time required for the interrupt processing constitutes a bottleneck for its execution. Therefore, there is a demand for the development of a more efficient system whereby the MAC unit
5
in the sub-processor
2
can be employed in common by the sub-processor
2
and the host processor
1
without any interrupt processing being required.
It is one object of the present invention to improve the operational performance of an integrated dual processor module by reducing the period of time required for the processing performed by a host processor.
It is another object of the present invention to provide an efficient system whereby a Multiply Accumulate (MAC) unit in a sub-processor can be employed in common by the sub-processor and a host processor.
SUMMARY OF THE INVENTION
To achieve the above objects, according to a first aspect of the present invention, a shared multiply accumulate (MAC) system comprises: a host processor; a sub-processor including multiply accumulate (MAC) unit; a host bus interface forming a connection between the host processor and the sub-processor; a first register set in which a multiplier, a multiplicand, a product and a status are written in order for the performance of a multiply accumulate (MAC) operation required by the host processor; a second register set in which a multiplier, a multiplicand, a product and a status are written in order for the performance of a multiply accumulate (MAC) operation required by the sub-processor; and selection means for selecting the first register set or the second register set upon receipt of a frequency division signal obtained by the division of an internal clock in the shared MAC system, wherein the MAC unit in the sub-processor performs the MAC operation in accordance with the contents of the first register set or of the second register set that is selected.
The selection means may include first selection means for, in response to the frequency division signal, supplying to the MAC unit a multiplier and a multiplicand written either in the first register set or in the second register set, and second selection means for, in response to the frequency division signal, supplying either to the first register set or to the second register set a product obtained by the MAC unit and a status.
The MAC unit is constituted by a multiplication unit and an addition unit.
It is preferable that the first and the second register sets be provided in the sub-processor.
According to a second aspect of the present invention, provided is a multiply accumulate (MAC) method for a shared MAC system that includes a host processor, a sub-processor having a multiply accumulate (MAC) unit, a host bus interface connected between the host processor and the sub-processor, and a register set, the MAC method comprising the steps of: writing a multiplier and a multiplicand to a register set via the host bus interface so that a multiply accumulate (MAC) operation required by the host processor can be performed; permitting the MAC unit, in response to a frequency division signal obtained by dividing an internal clock in the shared MAC system, to perform the MAC operation in a time sharing manner based on the multiplier and the multiplicand written in the register set; writing in the register set a product and a status obtained as a result of the MAC operation; and transmitting the product and the status via the host bus interface to the host processor.
The sub-processor, of which a high-speed repetitious MAC operation function is required, does not perform the MAC operation very frequently in general because the frequency at which the repetitious servo control function and so on are employed is relatively low. Thus, the MAC unit provided for the sub-processor is used in common in a time sharing manner as an external operating unit for the host processor. To do this, a host processor register set and a sub-processor register set are selectively connected to the MAC unit in accordance with a frequency division signal obtained by dividing an internal clock in the shared MAC system, and the MAC operation is performed.
REFERENCES:
patent: 4791590 (1988-12-01), Ku et al.
patent: 5204828 (1993-04-01), Kohn
patent: 5457804 (1995-10-01), Ohtomo
patent: 5771185 (1998-06-01), Miyake et al.
patent: 6148395 (2000-11-01), Dao et al.
Hattori Tetsuo
Matsumoto Yasuhiro
International Business Machines - Corporation
Malzahn David H.
Scully Scott Murphy & Presser
Underweiser, Esq. Marian
LandOfFree
Shared mac (multiply accumulate) system and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Shared mac (multiply accumulate) system and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shared mac (multiply accumulate) system and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2478608